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Datapath Design Engineer

Shanghai, Shanghai Municipality, China| Dalian, Liaoning, China Job ID JR0267672 Job Category Silicon Hardware Engineering Work Mode On-site Required Experience Level Experienced Full/Part Time Full Time
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Job Description


Intel Dalian Memory Technology and Manufacturing (DMTM) is high-volume manufacturing memory fab in Intel China working on leading edge 3D NAND product. Intel and SK Hynix have an agreement for SK Hynix to acquire Intel's NAND memory and storage business. and Intel will continue to manufacture NAND wafers at the Dalian memory manufacturing until the final closing expected to occur in March 2025. Intel DMTM will continue to build on the success of our NAND technology at a greater scale, play a larger role in supporting our customers.

Key Responsibilities:

Lead the design and development of data and I/O circuits for 3D NAND Flash memory products, focusing on achieving higher I/O speeds and optimal performance.
Architect and construct robust high-speed I/O solutions, ensuring they meet stringent area, power, and performance requirements within process limitations.
Oversee front-end and back-end high-speed I/O testing in post-silicon phases, ensuring product integrity and performance.
Collaborate closely with layout designers to optimize circuit area and performance, adhering to best practices in high-speed circuit design.
Interface with cross-functional teams to address and resolve product-level challenges, ensuring seamless integration and functionality

This position is associated with the sale of Intel's NAND memory and storage business to SK. This transaction will enhance the resources and potential of the business' storage, and you will be joining a world-class team that will transition to lead the SSD business at SK group. We will keep you informed updates and steps related to this transaction.


Qualifications


A Master or above degree in Electrical Engineering or a related field, with at least 3 years of experience in I/O design.
Proven expertise in RX, TX, and I/O pipeline circuit design and debugging.
Hands-on experience with DDR I/O interface training and calibration techniques.
A deep understanding of high-speed I/O circuit layouts and the intricacies of their design.
Knowledge of high-speed I/O operational mechanisms and associated reliability concerns.
Experience with power and signal integrity challenges in high-speed I/O domains.
Exceptional communication skills, with the ability to articulate complex technical concepts to peers and cross-functional teams.


Inside this Business Group


Employees in Intel's NAND Product Group deliver solutions that are transforming computing across all segments from data centers to Ultrabooks. They invent, develop, bring to market and support customers with leading-edge NAND flash memory and system level solutions such as solid state drives (SSDs). SSDs are accelerating performance for gaming enthusiasts, reducing total cost of ownership for IT managers of data centers and improving security and reliability for businesses. This dynamic group is strategically positioned to become the leading Non-Volatile Memory solution supplier for the compute segment and is a key to expanding markets and continuing the growth for Intel.

Other Locations



CN, Dalian


Posting Statement


All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits


We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.


Working Model


This role will require an on-site presence.
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