Engineering Program Manager

Hillsboro, Oregon, United States| Austin, Texas, United States| Phoenix, Arizona, United States| Folsom, California, United States| Santa Clara, California, United States Job ID JR0263618 Job Category Project and Program Management Work Mode Hybrid Experience Level Experienced Full/Part Time Full Time

Apply

Job Description

About the Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Foundry Technology Development (TD) is the heart and soul of Moore's Law at Intel. TD has enabled Intel to create world-changing technology that enriches the lives of every person on earth. TD's more than 10,000 employees drive breakthrough research, develop next generation process and packaging technologies, while also running high volume manufacturing operations in its state-of-the-art facilities in Oregon and Arizona. You will be a key member of the Design Enablement customer application and support team and will own significant customer enablement tasks in a fast-paced and technically challenging environment.

Responsibilities as the Technical Program Manager in our Foundational IP (FIP) Enablement and growing Support organization will include:

- Working closely with FIP Product and Application Engineering teams to ensure that programs are successfully executed against established technology platforms and commitments in memory compilers, custom memories, analog and mixed signals IPs and standard cell libraries.

- Performing as the focal point of communication for customers, internal cross-functional teams and managers across several time zones, ensuring schedule, priorities alignment and steering risk management plans.

- Establishing continuously improvement processes for customer feedback and communication, IP and applications release planning, managing support issues, and improving our FIP offering.

#Design Enablement

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Candidate will possess a BS degree with 6+ years of experience or MS degree with 4+ years of experience or PhD degree with 2+ years of experience in Electrical Engineer or Computer Engineering or related STEM field.

In addition to minimum degree and experience, you will have 8+ years of relevant experience in:

Cross-functional and program management track record working in SoC, IP design or closely related domains.
Project management techniques and application experience managing several projects while executing milestone delivery schedules using Agile, Waterfall, etc.
Soc design methodology, FIP, IC and manufacturing process technology knowledge.
Background establishing continuous improvement program management practices.
Experience communicating and reporting updates to senior management within an organization and customers.

Preferred Qualifications:

EDA tools from Cadence, Mentor Graphics, or Synopsys.
Advanced manufacturing process nodes.
Experience or knowledge in FIP ecosystem and standard engineering practices.
Background experience in a foundry or EDA industry.
Jira Software and Jira Service Management.
Customer orientation and experience with prioritization and execution under pressure.

Inside this Business Group

Other Locations

US, TX, Austin; US, AZ, Phoenix; US, CA, Folsom; US, CA, Santa Clara

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.

Annual Salary Range for jobs which could be performed in US, California: $162,041.00-$259,425.00
*Salary range dependent on a number of factors including location and experience

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.

Apply

Maggie Offensive Security Researcher

“I’ve always wanted to do something that changes the world — at Intel, I feel appreciated, and I’ve gained more confidence in myself. It makes me feel like I’m capable of doing great things.”

Pre-silicon system integration engineer Multiple Locations View job
Junior Manual QA Engineer Tel Aviv, Israel View job
Solutions and Services Category Planning and Launch, NEX Sales Santa Clara, California View job