DFT Design Engineer

Allentown, Pennsylvania, United States| Austin, Texas, United States| Santa Clara, California, United States Job ID JR0262880 Job Category Silicon Hardware Engineering Work Mode Hybrid Experience Level Experienced Full/Part Time Full Time

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Job Description

Do Something Wonderful!

Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let’s do something wonderful together. Join us, because at Intel, we are building a better tomorrow. Want to learn more? Visit our YouTube Channel or the links below!

The Network and Edge group (NEX) at Intel drives the software-defined transformation of the world's infrastructure - in data centers, in networks, and at the edge. We are a team of problem solvers, experimenters, and innovators who are dedicated to designing the network technologies that currently lead and continue to transform data-center and AI ecosystems.

Exciting opportunity to be a part of XNE DFT team.

The Design-for-Test (DFT) Implementation Engineer is a challenging and cutting-edge position working as part of a team to implement Design-for-Test capabilities on state-of-the-art silicon designs. You will be working with both external tier-1 customers and internal product design teams during their ASIC design cycle as they develop System-on-a-Chip (SoC) solutions utilizing CMOS cell-based ASIC technologies, along with integrated high-performance SerDes functions, embedded microprocessors, and high-speed memory interface IP.

You will be responsible for development of the SoC Test Implementation plan describing the strategies to address the DFT requirements for the design, planning of the hierarchical test architecture, insertion of DFT structures, generation, simulation, and validation of test patterns for both DFT logic verification and for HVM ATE testing of the design, supporting the Static Timing Analysis (STA) team for the timing closure for the DFT modes of the design, and for supporting the Test Engineering team during silicon bring-up. You will also work closely with internal Test Methodology team and IP development teams.

The DFT Engineer should possess the following behavioral traits.

Excellent teamwork skills including ability to work with multiple and remote groups worldwide.
Motivated self-starter, with strong ability to work independently as well as in a team environment.
Strong verbal and written communication skills in English.
Flexibility and maturity in facing uncertainties and changing priorities/responsibilities.
Act with velocity and a strong sense of urgency.
Respect cultural diversity and sensitivity.
Agility in learning, improving, and innovating.

Qualifications

What we need to see (Minimum Qualifications):

Master's degree in electrical or computer engineering with 3+ years of industry experience or bachelor's degree with 4+ years of industry experience.
4+ years of experience in Design-For-Test (DFT) principles such as SCAN for logic testing, BIST and repair for memory test, or JTAG Boundary SCAN.
4+ years of experience in Test insertion, test pattern generation, simulation, and verification. 6+ years of experience in Industry-standard DFT tools such as Mentor Graphics Tessent, Synopsys DFT Compiler, DFTMax, TetraMax.

How to Stand out (Preferred Qualifications):

Master's degree in electrical or computer engineering with 8+ years of industry experience or bachelor's degree with 10+ years of industry experience.
Knowledge of manufacturing tester capabilities, Automatic Test Equipment (ATE), and test program experience
Knowledge of DFT integration of IP (e.g. DDR, SerDes, PLL's) into an SoC
Static Timing Analysis, Synopsys PrimeTime, constraints and timing path debug
Scripting Languages, e.g., PERL, TCL/Tk, Python.
DFT architecture development and planning for an SoC

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Amazing Benefits!

Here at Intel, we invest in our people. Beyond health, dental, and retirement benefits, Intel’s benefits package includes 14 paid holidays per calendar year, three weeks of paid vacation, and four-week paid sabbatical every four years of employment. Intel also offers employees five bonuses per year dependent on overall company and personal performance, and an employee stock purchase program. Find more information about our Amazing Benefits here: https://jobs.intel.com/benefits

Inside this Business Group

Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.

Other Locations

US, TX, Austin; US, CA, Santa Clara

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.

Annual Salary Range for jobs which could be performed in US, California: $123,419.00-$185,123.00
*Salary range dependent on a number of factors including location and experience

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.

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