Analog Design Engineer

San José, Provincia de San José, Costa Rica Job ID JR0262464 Job Category Silicon Hardware Engineering Work Mode Hybrid Experience Level Experienced

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Job Description

We are looking for a highly motivated analog design engineer to join the IP, Security and Client Product Group (ISCP) Circuits team for Intel's next generation of chipsets/SOC.

As part of the team, you will be working across different teams within the organization: architecture, technology development, IP designers, package and platform engineers to design and integrate best in class Hard IPs.

Responsibilities for this role include, but are not limited to:

Design, simulation, characterization, and integration of on-die power delivery circuits such as: LDOs, power gates, voltage monitors.
Work with architecture team to define and deliver the next generation of Hard IPs for future SOCs.
Design, simulation, characterization and integration of circuits and components such as PLLs, DLLs, system monitors: thermals, voltage, clock.

Behavioral traits:

Willing to work effectively both independently and as a team.
Technical leadership with good communication skills.
Advanced interpersonal and problem-solving skills.
Willing to work across the organization to achieve goals and thrive in a team-orientated environment.

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your
schoolwork/classes/research and/or relevant previous job and/or internship experiences.

Minimum Qualifications
The candidate must have a bachelor's degree in electrical/computer engineering or related field and 3+ years; OR master's degree in electrical/computer engineering or related field and 2+ years of experience in:

Analog circuits design.
Solid foundation knowledge of SOC design, timing analysis and reliability analysis.
Advanced English level.

Preferred Qualifications

PhD in Electrical/Computer Engineering or related field.
2+ years of experience working with mixed signal design and post-silicon debug.

Inside this Business Group

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations. DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.

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Maggie Offensive Security Researcher

“I’ve always wanted to do something that changes the world — at Intel, I feel appreciated, and I’ve gained more confidence in myself. It makes me feel like I’m capable of doing great things.”