Power Integrity Engineer

San Diego, California, United States| Hillsboro, Oregon, United States| Austin, Texas, United States| Phoenix, Arizona, United States| Folsom, California, United States| Santa Clara, California, United States Job ID JR0262126 Job Category Platform Hardware and Systems Engineering Work Mode Hybrid Experience Level Experienced

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Job Description

Do Something Wonderful!

Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let’s do something wonderful together. Join us, because at Intel, we are building a better tomorrow.

Are you passionate about ensuring high-quality power integrity solution in cutting-edge heterogeneous SoCs for high-power discrete graphics products? If yes, we have an exciting opportunity for you as a power integrity technical lead at Intel's client graphics and AI group.

This Power Integrity Engineer position involves research, pathfinding, implementation, analysis, validation and sign-off of power distribution network (PDN) including monolithic and heterogenous SoCs, package substrate, PCB and VRM. You will work with multi-functional teams to drive the development of advanced droop mitigation schemes, develop PI methodology and automation, quantify benefits of various circuit schemes through end-to-end PDN simulations, provide design guidelines and requirements to platform, package and SoC/IP teams ensuring robust integrations.

Additional areas of responsibility for this role include, but are not limited to the following:

Develop and analyze power delivery networks including 2D and 3D model extraction and noise analysis across die/C4 bumps, silicon, package, sockets, and boards
Collaborate with the silicon integration team, die floor planners, package and PCB design teams to optimize the on-die decoupling partitions and implement the package/PCB decoupling scheme and voltage regulation for package/die
Define power grid specification and power and area targets to achieve the best balance of power integrity and performance
Derive platform level specifications from silicon specifications, ensure package/platform pathfinding to converge on feature set/form factor, and VR performance, characterization
Performs measurements to characterize power noise profile across frequency, ground bounce, and other key metrics to verify power delivery network after design and correlate back to pre-silicon models
Adhere to project timelines and deliver high-quality work within specified deadlines

Behavioral skills we are looking for:

Good communication skills and ability to document and share findings with others

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Bachelors Degree in Electrical Engineering, Computer Engineering or related STEM degree and 5+ years industry experience, OR

Masters Degree in in Electrical Engineering, Computer Engineering or related STEM degree and 4+ years industry experience, OR

PhD Degree in in Electrical Engineering, Computer Engineering or related STEM degree an 2+ years industry experience

Plus relevant years of experience in all of the following skills:

Familiar with Die, package, PCB and VRM power delivery
Knowledge of Silicon, Package and PCB layouts and PDN design practices
Good understanding of various droop mitigation schemes, Verilog level modeling, On-chip PDN and circuit techniques, PDN to timing validation and correlation
Expertise in circuit simulation with Spice, Virtuoso and EM extractions with commercially available solvers from Ansys, Cadence, Synopsys and Keysight
Solid scripting skills in Python/Tcl

Preferred Qualifications:

Design, modeling and analysis experience of on-chip droop mitigation, LDO techniques, die/package/PCB PDN
Experience with transmission line theory and electromagnetic field theory
Package and PCB design tools from Cadence and Mentor
Power converter topologies and control schemes

Inside this Business Group

The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

Other Locations

US, OR, Hillsboro; US, TX, Austin; US, AZ, Phoenix; US, CA, Folsom; US, CA, Santa Clara

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.

Annual Salary Range for jobs which could be performed in US, California: $123,419.00-$185,123.00
*Salary range dependent on a number of factors including location and experience

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.

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