Senior Defect Control and System Engineer

Kiryat Gat, Southern District, Israel| Leixlip, Leinster, Ireland Job ID JR0255646 Job Category Manufacturing and Process Development Work Mode Hybrid Experience Level Experienced

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Job Description

Fab Sort Manufacturing (FSM) is responsible for the production of all Intel silicon using some of the world's most advanced manufacturing processes in fabs in Arizona, Ireland, Israel, Oregon and 2 new greenfield sites in Ohio and Germany.

As part of Intel's IDM2.0 strategy, FSM is rapidly expanding its operation to deliver output for both internal and foundry customers with state-of-the-art technologies arriving in high-volume manufacturing at a 2-year cadence going forward.

Intel recently created HVM Global Yield organization in FSM to strengthen its yield operation and enable fast-paced yield ramp-up in early HVM phases for each technology in collaboration with Technology Development team and FSM fab managers.

This job requisition is to seek Defect Metro engineering roles in FSM HVM Global Yield organization, reporting to Defect Metro team manager.

We are looking for Defect Control Engineers with Strong data analysis and programing skills (SQL/Python/MATLAB).

Selected candidates will work with other members in Global Yield org including Process Integration, Yield Analysis and Device Integration teams, fab module/yield teams and TD team members to achieve yield ramp-up and process optimization in early production stage, supporting internal and external customers.

Defect Control engineers' responsibilities include (but not limited to):

Collaborate with Technology Development team and Process Integration team members to import and setup new technology to production fabs.
Strong data analysis and programing skills - AI/Machine learning, Programming (SQL/Python/MATLAB), Software Development, Data Visualization
Set up and optimize wafer inspection steps and recipes, to ensure detection of yield detracting defects in line at step.
Experience in Image process and big data analysis.
Work with Defect Metro engineers to optimize and identify the best inline defects detectability on the silicon wafers.
Execute and produce wafer inspection strategy to protect yield and quality at maximum productivity and lowest cost.

Candidate should possess the following behavioral skills:

Problem-solving technique with strong self-initiative and self-learning capabilities. Ability to work with multi-functional, multi-cultural teams.
Must demonstrate solid written and verbal communication skills.

#foundry

Qualifications

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Bachelor's degree in science and engineering major.
Strong data analysis and programing skills:
Advanced programming and program-debug skills, Python being the ideal area of expertise.
AI/Machine learning, Programming (SQL/Python),
Data Visualization.

Preferred Qualifications:

Advanced degree (Master's or Ph.D.) in Physics or Materials Science major.
Hands-on experience in advanced node semiconductor industry in Defect engineering or Failure analysis.
3+ years' experience with defect inspection tools in high-volume semiconductor manufacturing.
3+ years' Hands-on experience in wafer inspection recipe setup and optimization.
3+ years' experience with layout-sensitive defects and knowledge of scan diagnosis and other defect analysis skills.
Experience in new semiconductor technology development.
Basic understanding and collaboration experience with module processes including lithography, dry etch, wet etch, CMP, diffusion, implant, thin films and metrology.

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Other Locations

IE, Leixlip

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.

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Maggie Offensive Security Researcher

“I’ve always wanted to do something that changes the world — at Intel, I feel appreciated, and I’ve gained more confidence in myself. It makes me feel like I’m capable of doing great things.”