Memory IP Enablement Manager

Hillsboro, Oregon, United States| Austin, Texas, United States| Phoenix, Arizona, United States| Folsom, California, United States| Santa Clara, California, United States Job ID JR0263619 Job Category Silicon Hardware Engineering Work Mode Hybrid Experience Level Experienced Full/Part Time Full Time

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Job Description

About the Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Foundry Technology Development (TD) is the heart and soul of Moore's Law at Intel. TD has enabled Intel to create world-changing technology that enriches the lives of every person on earth. TD's more than 10,000 employees drive breakthrough research, develop next generation process and packaging technologies, while also running high volume manufacturing operations in its state-of-the-art facilities in Oregon and Arizona. You will be a key member of the Design Enablement customer application and support team and will own significant customer enablement tasks in a fast-paced and technically challenging environment.

As a team manager in a new and growing organization you will focus on:

- Memory segment of our technology platform, including memory compilers and custom embedded memories.
- Establish and evolve organizational processes, prioritizing removal of obstacles from our internal and external customer's path and delivery of the best-in-class technology platform.

- Collaborate with the Technical Program Management team to ensure clear prioritization, scheduling and load balancing across the team.

- Provide technical and management guidance to the team, identify expertise gaps and collaborate with the Ops and Training organizations on the team's upskilling program.
- Review and develop design technology solutions and support to meet customer requests in areas including, but not limited to Memory Compiler Design Flow and Methodology development, custom memory IP, RTL, and characterization of Memory Compilers. IP acceptance QA/SOC integration testing.
- Leverage your technical experience in SoC design and understanding of IC manufacturing process.

- FIP development, QA and EDA ecosystem.

#Design Enablement

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Candidate will possess a BS degree with 6+ years of experience or MS degree with 4+ years of experience or PhD degree with 2+ years of experience in Electrical Engineer or Computer Engineering or related STEM field.

In addition to minimum degree and experience, you will have 9+ years of relevant experience in:

Building organizations and evolving organizational capabilities in one or more of the following domains: SoC, ASIC, IP or FIP design, Application Support Engineering for EDA or IP, DTCO, process technology development.
Knowledge or experience in Memory FIP ecosystem and standard engineering practices (Reliability/Variation/Low Power Design).
Memory Compiler and Embedded Custom Memory design knowledge.
Knowledge of Soc design methodology, FIP, IC manufacturing and process technology.
Experience or background establishing continuous improvement processes.

Preferred Qualifications:

Technical skills working within cross-functional teams and Technical Program Management.
Experience managing Application Support Engineers and teams within EDA or IP design domains.
Jira Software and Jira Service Management experience.
Prioritization and execution experience.
Project management techniques experience in Agile, Waterfall, etc.
Advanced experience or knowledge in process nodes.
Working experience in a foundry or EDA industry.

Inside this Business Group

Other Locations

US, TX, Austin; US, AZ, Phoenix; US, CA, Folsom; US, CA, Santa Clara

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.

Annual Salary Range for jobs which could be performed in US, California: $141,673.00-$241,005.00
*Salary range dependent on a number of factors including location and experience

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.

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Maggie Offensive Security Researcher

“I’ve always wanted to do something that changes the world — at Intel, I feel appreciated, and I’ve gained more confidence in myself. It makes me feel like I’m capable of doing great things.”

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