Applications Engineer Physical Design/Fill - (Design Enablement)

Hillsboro, Oregon, United States| Phoenix, Arizona, United States| Santa Clara, California, United States Job ID JR0262670 Job Category Software Engineering Work Mode Hybrid Experience Level Experienced

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Job Description

At Intel, Design Enablement (DE) is one of the key pillars enabling Intel to deliver winning products in the marketplace. You will directly drive and work with DE cross teams to ensure that design-kits for customer enablement are lead cutting edge technologies. In addition, you will work with our customers to outline and collaborate on requirements with internal partners to define the scope, execution planning, and competitive solutions to meet the customer's needs.

This position's supporting role will drive solutions for ASIC tools/flows when customers use intel PDK collaterals in Physical design domain. You will also lead the collaboration across ourTD/DE/QnR organizations to find the best path to resolve the issue, along with owning/maintaining training documents, user guide, and customer ticket support.

As a DEAS (Design Enablement Application and Support) key member, you will use your communication skills to interact with customers directly while applying analytical problem-solving capability to identify the key requests, root-causing the issue, and teamwork with DE stakeholders to support and enable the customer's success.

#DesignEnablement

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Candidate must possess a BS degree with 4+ years of experience or MS degree with 3+ years of experience or PhD degree with 1+ years of experience in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering or a related field.

5+ years of experience in two or more of the following areas:

- Intel and/or external foundry process technology knowledge in advance nodes
- Exposure to layout, schematic entry using Cadence Virtuoso and Synopsys Custom Designer
- Development/support or handling of issues pertaining to DRC, LVS, antenna, density and fill on foundry process technology
-Exposure to one or more EDA tools on fill related issues (Synopsys ICV, Cadence Pegasus, Siemens Calibre)

Preferred Qualifications:

- Experience and background in analytical problem-solving to identify the key requests and root-causing the issue.

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Other Locations

US, AZ, Phoenix; US, CA, Santa Clara

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.

Annual Salary Range for jobs which could be performed in US, California: $123,419.00-$185,123.00
*Salary range dependent on a number of factors including location and experience

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.

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Maggie Offensive Security Researcher

“I’ve always wanted to do something that changes the world — at Intel, I feel appreciated, and I’ve gained more confidence in myself. It makes me feel like I’m capable of doing great things.”