Skip to main content
Search jobs

SoC Design Engg - SD SignOff

Bengaluru, Karnataka, India Job ID JR0251992 Job Category Silicon Hardware Engineering Work Mode Hybrid Experience Level Experienced Full/Part Time Full Time
Apply

Job Description


  • We are looking forward to candidates with:
    In this position you will be responsible for Performance Verification (PV)/STA including timing analysis, noise glitch analysis for leading-edge designs.
    Development and validation of constraints for blocks, subFC and Full Chip
    Understanding of IO/ACIO timing closure
    Understanding of Synthesis , DFT insertions that include MBIST and SCAN.
    Timing execution and signoff convergence for func and test modes
    PTECO/Tweaker ECO flow and timing convergence
    Work closely with process technology team to understand process characteristics and set appropriate constraints in timing analysis flows and methodology.
    Interact with SoC customers to understand IP/SoC interface design requirements/objectives and develop appropriate interface signoff constraints for IPs.
    Mentor junior design engineers to build a capable team.

Qualifications


  • Qualifications

Experience : Should have 5+ years of experience in relevant field
Bachelor Degree in Electrical and Electronics Engineering or Master Degree in Electrical and Electronics Engineering or Computer Engineering
Good understanding of overall ASIC Physical Design/DFT, Tools and implication on Timing Convergence
Must have understanding of relevant areas of Library / Memory / Other collaterals and dependencies on STA
Must understand Ultra Submicron issues, Variation aware/Aging Aware Design Sign-off Must understand CTS/Other clock Distribution methodologies well.
Teamwork / flexibility / ability to thrive in a dynamic environment are very important

              Strong Communications skills and the ability to effectively work with cross functional teams.


Inside this Business Group


Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.


Posting Statement


All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits


We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.


It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel’s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at https://jobs.intel.com/ and not fall prey to unscrupulous elements.

Working Model


This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
Apply
Maggie, Offensive Security Researcher

Maggie Offensive Security Researcher

“I’ve always wanted to do something that changes the world — at Intel, I feel appreciated, and I’ve gained more confidence in myself. It makes me feel like I’m capable of doing great things.”

  • Communications Specialist/Technical Writer Multiple Locations View job
  • PDK Extraction Runset Developer Multiple Locations View job
  • EDA Tools Hardware Engineer Multiple Locations View job
View all jobs

You don't have Recently Viewed Jobs yet.

View all jobs

You don't have Saved Jobs yet.

View all jobs

Join Our Talent Community

Be the first to hear about what's happening at Intel! Sign up to receive the latest news and updates.

Sign up