IP Design Verification Engineer

Bengaluru, Karnataka, India Job ID JR0263808 Job Category Silicon Hardware Engineering Work Mode Hybrid Experience Level Experienced Full/Part Time Full Time

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Job Description

The IFS Silicon Engineering MSIP team is responsible for enabling High Speed Serdes IP development which includes interaction with SoC for high level spec definition, logic design and verification, FPGA rapid prototyping validation and sub-system level controller interoperability verification and post silicon debugging. IP Sr Verification Lead shall be responsible for leading a small team of verification engineers who shall be part of a highly motivated verification team which is responsible for DV for IPs like UCIe, HBM, Aphy, PCIe, UFS etc. List of responsibilities includes but not limited to the following tasks. Prepare and implement a robust end to end / comprehensive RTL verification test plan for IP verification. Develop any needed verification /regression enabling automation tools / methods / flows as needed. Be familiar with SerDes architecture implementation and prepare and implement IP/sub system level test bench along with relevant test cases (directed / randomized)with appropriate assertions and drive to meet set coverage goals. Be familiar with RAL standards for register validation. Be familiar with NLP flows for UPF based low power verification and GLS flows. Be familiar with verification of industry standard micro controllers like Xtensa/ARC EM uControllers which are used for high speed channel receiver adaptation / calibration. Set clear expectations of coverage metrics vis-a-vis code coverage / functional / feature driven coverage and drive to achieve the same. Possess sharp test content creation, debugging skills and file for bugs and close on them in a timely fashion. Work with cross functional teams on enabling FPGA prototypes for emulation and or post silicon debug.

Qualifications

BE/ME/MTech/MS with 6 to12 years of SerDes RTL verification experience. Must be well versed in using advanced verification methodologies like UVM/OVM/VMM/System Verilog, constrained random stimulus generation, assertion based verification and functional coverage techniques. Must be well versed in RAL standards, NLP/GLS verification flows. Experience in IP level and sub-system level verification on protocols like PCI-E , UCIe, HBM, UFS is a strong plus. Having relevant experience in enabling and verifying controller interoperability testing at sub system level is a plus. Familiarity with RTL design aspects like Physical Coding sub layer, Physical media access blocks is a strong plus. Basic familiarity with high level advanced receiver adaptation techniques which may include fsm or ucontroller based firm- ware driven equalization is a strong plus. Basic Knowledge of real value modelling of channel impulse response for receiver adaptation / equalization verification is a strong plus.

Inside this Business Group

Intel Foundry is dedicated to transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. As stewards of Moore's Law, we innovate and foster collaboration within an extensive partner ecosystem to advance technologies and enable our customers to design leadership products. Our strategic investments in geographically diverse manufacturing capacities bolster the resilience of the semiconductor supply chain. Leveraging our technological prowess, expansive manufacturing scale, and a more sustainable supply chain, Intel Foundry empowers the world to deliver essential computing, server, mobile, networking, and automotive systems for the AI era. This position is part of the Foundry Services business unit within Intel Foundry, a customer-oriented service organization that is dedicated to the success of its customers with full P&L responsibilities. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.

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Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.

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Maggie Offensive Security Researcher

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