Semiconductor Device Modeling Engineer

Job Description

About the team and organization: Compact Device Modeling Group (CDMG) is part of Intel's Design Enablement (DE) organization. DE is a key pillar in enabling Intel to deliver design, development and manufacturing services that allow internal and external customers to deliver winning products to the marketplace. Your work will directly enable design teams to get to the market faster with leadership products based on innovative technologies. As a member of CDMG you will be at the forefront of co-optimizing Intel's state-of-the-art process technology which allows customers with diverse design needs to enable best-in-class products for data-centric applications.

As a semiconductor device modeling engineer, you will be responsible to characterize device behavior and generate/update device models for new technologies, ensure robustness and accuracy of model simulation.

Qualifications

Minimum Qualifications:

• A Master's degree in electrical engineering or related discipline, with a minimum of 5+ years of industry experience in the semiconductor field. Or a PHD in electrical engineering or related discipline, with a minimum of 1 years of experience and a dissertation focused on semiconductor devices or processes.

• Minimum of 1 years of Experience in BSIM models and other compact models, extraction tools (ICCAP or MBP), and commercially available simulators example: HSPICE, SPECTRE, etc.)

• Understanding of corner, statistical and sub-circuit models and their usages.

• Understanding of layout effects and models.

• Hands-on experience in Python or C, Shell programming.

• Experience or course work in semiconductor device physics, process flow, layout and simple circuit design and simulation.

• The ability to work independently after the initial ramp-up time.

Preferred Qualifications:

• A Ph.D. degree in electrical engineering or related discipline with 5 + years of industry experience in the semiconductor field.

• Understanding of basic analog and digital circuit blocks and model interaction.

• Hands-on experience in semiconductor device DC/CV characterization tools, techniques, and systems. Experience in test automation and RF/noise/reliability tests is a plus.

• Understanding of Aging Simulations and reliability methodologies and tools is a plus.

• Experienced in a Cadence design environment, including schematic capture, analog design environment, virtuoso layout design, DRC, LVS, and layout extractions.

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Other Locations

TW, Taipei

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.