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Senior IP Design Verification Engineer

Pulau Pinang, 马来西亚| Kulim, 吉打, 马来西亚 職位 ID JR0266496 職位類別 Silicon Hardware Engineering 工作模式 Hybrid 經驗級別 Experienced 工时类型 全職
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Job Description


We believe the world needs technology that can enrich the lives of every person on earth. We’re inviting dynamic and imaginative technocrats to take part in creating it.

PMC (Power Management Controller) team is responsible for delivering power management, survivability and other services in today's AI (Artificial Intelligence) PC. PMC is one of the critical core functions in System-on-Chip (SoC) in handling multiple chiplets in industry-leading edge die-disaggregation technology.

Our development activities include micro-architecture, firmware (FW), hardware (HW) design and pre-silicon verification.

As part of the PMC IP design verification team, you will get the opportunity to work on most advanced leading technology with the platform and IP architects/micro-architects while defining and developing the verification content for PMC HW and FW. Besides this, there is opportunity to participate in continuously looking into contemporary methodology on HW-FW co-validation and various tools with AI to improvise our efficiency. Our team also focuses on individual development plans as career growth path and team building activities to strengthen the validation team bonding.

Core responsibilities will include:

  • Defining validation strategy, developing test plans, tests, checkers and modelling to verify PMC hardware and firmware.

  • Analyzing test failures and implementing corrective measures.

  • Utilizing various tools and methodologies and Artificial Intelligence (AI) with the goal to ensure HW/FW correctness and to improve efficiency/coverage.

  • Communicating effectively and coordinating with designers and architects.


Qualifications


  • Bachelor's or Master's degree in Electrical/ Electronic/ Computer Engineering or related field with at least 5 years of experience.

  • In depth knowledge of language such as System Verilog/Verilog, and of industry standard tools and methods such as VCS/Verdi, OVM/UVM, Formal Verification.

  • Experienced in IP design, IP validation or hardware-firmware co-validation.

  • Interpreting Technical specs, Firmware and RTL design.

  • Computer architecture and Power management knowledge is a plus.

  • Behavioral traits like problem solving, teamwork, commitment to task and quality focus.


Inside this Business Group


In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations.  DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Other Locations



MY, Kulim


Posting Statement


All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits


We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.


Working Model


This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change...
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