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CPU Physical Design Automation Engineer

奧斯汀, 德克萨斯州, 美国 職位 ID JR0268641 職位類別 Silicon Hardware Engineering 工作模式 Hybrid 經驗級別 Entry Level 工时类型 全職
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Job Description


Do Something Wonderful!

Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow.

Who We Are

The E-core CPU team is powered by some of the brightest and most innovative minds in the industry and we need you. Intel has a vision to create and extend computing technology to connect and enrich the lives of every person. We are designing future generations of high-performance E-core CPUs using the most advanced and innovative process technologies. If you are looking to grow and develop your skillsets while be surrounded by highly motivated and knowledgeable teammates, then this is the organization for you.

E-Core CPUs are the industry leading performance per watt CPU that helps:

  • Power the latest Intel laptops, desktops and high-end gaming platforms.

  • Drive 5G communications by serving as the base-station that delivers essential data from your electronic devices across the world at maximum bandwidth.

  • Create Artificial Intelligence (AI) and machine learning devices.

  • Enables a full virtual learning experience for students using the latest Google Chromebooks

Who You Are

As a CAD Physical Design Engineer in the E-core CPU group, you will be responsible for:

  • Developing, debugging, and supporting tools, flows and methodologies covering backend physical design methodologies and flow automation for high performance blocks and full chip level using RTL2GDS standard cell level design techniques.

  • Performing analysis of either synthesis, place and route, floor planning or signoff for static timing analysis on timing paths, formal equivalence verification, power consumption, electrical rule checking and circuit reliability to identify key issues.

  • Working closely with design teams to understand and debug tool issues and constraints.

  • Working with industry EDA vendors to build and enhance tool capabilities to design a high-speed, low-power synthesizable CPU.

  • Creating documentation and help with guidelines/specs.

  • Communicate with other team members to solve problems and following solutions through to completion Excellent verbal and written English communication skills


Qualifications


You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork/classes/research and/or relevant previous job and/or internship experiences.

Minimum Qualifications

  • Bachelor's Degree in Computer Engineering and/or Electrical Engineering and 2+ years of relevant working experience OR Master's Degree in Computer Engineering and/or Electrical Engineering in Computer Engineering and/or Electrical Engineering OR

  • Coursework and/or 3+ months experience in VLSI, design automation algorithms, and transistor-level design

  • Coursework and/or 3+ months experience using industry standard Engineering Design Automation (EDA) VLSI tools/flows from vendors such as Synopsys, Cadence and/or Mentor Graphics for performing synthesis, place-and-route, extraction, timing/power analysis and functional verification.

  • 1+ years’ experience with Python, Perl, and/or Tcl scripting languages.


Preferred Qualifications

  • 1+ years of relevant working experience in microprocessor or other high speed design backend design.

  • Experience with timing closure methodology for worst-case corner (static timing analysis / STA, statistical variation analysis, spice circuit simulation, ERC, noise analysis flows, cross talk, OCV effects, budget constraints)


Inside this Business Group


The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.


Posting Statement


All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits


We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.



Annual Salary Range for jobs which could be performed in the US $91,500.00-$137,436.00
*Salary range dependent on a number of factors including location and experience


Working Model


This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change...
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