DFT Design Engineer

Job Description

Do Something Wonderful!

Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow.

Who We Are

Do you want to collaborate with the best minds in the world? Are you passionate about AI and its potential in transforming the future of computing? Join our world-class SOC design team within the Xeon Engineering Group (XEG) delivering on next-generation Xeon and AI products.

Who You Are

Your job responsibilities will include but not limited to:

• Developing the logic design, register transfer level (RTL) coding, simulation, and DFT timing closure support as well as test content generation and delivery to manufacturing for various DFx content (including SCAN, MBIST, and BSCAN).

• Participates and collaborates in the definition of architecture and microarchitecture features of the block, subsystem, and SoC under DFT being designed (including TAP, SCAN, MBIST, BSCAN, proc monitors, in system test/BIST).

• Develops HVM content for rapid bring up and ramp to production on the automatic test equipment (ATE). Applies various strategies, tools, and methods to write and generate RTL and structural code to integrate DFT.

• Optimizes logic to qualify the design to meet power, performance, area, timing, test coverage, DPM, and test time/vectormemory reduction goals as well as design integrity for physical implementation.

• Reviews the verification plan and drives verification of the DFT design to achieve desired architecture and microarchitecture specifications.

• Ensures design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.

• Integrates DFT blocks into functional IP and SoC and supports SoC customers to ensure high quality integration of the IP block.

• Collaborates with post silicon and manufacturing team to verify the feature on silicon, support debug requirements, and document all learnings and improvements requirement in design and validation.

• Drives high test coverage through structural and specific IP tests to achieve the quality and DPM objectives of the product and develops HVM content for rapid bring up and production on the ATE.

Qualifications

Minimum Qualifications

• Bachelor’s degree in Computer or Electrical Engineering, or a related field with a year of related experience OR Master's degree in Computer or Electrical Engineering, or a related field

• 1 year experience with test architecture

Preferred Qualifications

6+ months experience with:

• GLS to resolve stuck-at and at-speed test scenarios

• ATPG coverage analysis

• EDT configuration setup

• TCL, Python, Perl and/or C++ programming

Inside this Business Group

Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.



Annual Salary Range for jobs which could be performed in the US $91,500.00-$137,436.00
*Salary range dependent on a number of factors including location and experience

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.