Analog Layout Design Engineer

Job Description

• Provide support and develop solutions to enhance the productivity of design engineers with a strong focus on analog layout design methods.

• Work with EDA vendors and Intel design automation team to evaluate and stay up to date on the latest tools and features.

• Support tools, flows, and methods on new process technologies.

• Represent DDG for aligning its IP design needs with the latest tech file and design environment releases ensuring design environments are evaluated and ready for design team to execute.

• Work with corporate IT and compute infrastructure teams to ensure DDG design teams have compute and disk resources that meet the needs of the latest tools and methods.

• Develop regression suits to test new tool, flow, and methodology solutions and apply metrics to track acceptance and efficiency improvements.

• Facilitate training for DDG design teams on tools, flows, methods, and process technologies. 

• Self-motivator with strong problem-solving skills

• Willingness to work with teams across projects, domains, and geos

• Effectively working with customers and excellent interpersonal skills

• Effectively communicate with larger numbers of design and layout engineers, providing high quality documentation and presentations.

Intel invests in our people and offers a complete and competitive package of benefits employees and their families through every stage of life. 

See https://www.intel.com/content/www/us/en/jobs/benefits.html for more details. 

Qualifications

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

• 4+ years of experience in the following:
    -Supporting analog design workflows and working with EDA tools like Cadence
    - Virtuoso or Synopsys Custom Compiler with an understanding of analog and mixed signal design
    - Programming and scripting (Perl, SKILL, Tcl, or shell)

• Experience with backend verification and signoff (DRC, LVS, Calibre, ICV, RV, ESD)

• Knowledge and understanding of training development and delivery

• Knowledge of Constraints driven designs and flows

Inside this Business Group

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations.  DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.



Annual Salary Range for jobs which could be performed in the US $144,501.00-$217,311.00
*Salary range dependent on a number of factors including location and experience

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.