SoC RTL Designer Engineer

You will be responsible for designing and/or integrating IP for a discrete graphics SoC. You will be working or assisting in architecture, design, implementation, formal verification, emulation and validation of discrete graphics SoC products, including: 

• Creating a design to produce key assets that help improve product KPIs for discrete graphics products 

• Working with SoC Architecture and platform architecture teams to establish silicon requirements 

• Making appropriate design trade off balancing risk, area, power, performance, validation complexity and schedule 

• Creating micro architectural specification document for the design. 

• Working with external vendors on tools or IPs required for the development of micro-architecture, design and design qualification of custom silicon designs.  

• Driving vendor's methodology to meet world class silicon design standards 

• Architecting area and power efficient low latency designs with scalabilities and flexibilities 

• Power and Area efficient RTL logic design and DV support 

• Running tools to ensure lint-free and CDC/RDC clean design, VCLP 

• Synthesis and timing constraints 

Behavioral traits that we are looking for:

• Good communication and collaboration skills

• Possess strong teamwork, problem-solving and influencing skills along with abilities to work with different geographical locations

• Ability to work independently and proactively to lead technical activities

• Ability to work well in a team and be productive under ambitious schedules 

• Should be self-motivated and well organized 

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Must have a Bachelor's Degree in Computer Engineering, Computer Science, Electrical Engineering or similar STEM degree with 5+ years of industry experience in three or more of the following:

• Lint tools, CDC and RDC tools, timing constraints, fishtail. 

• Experience with Verilog and system Verilog, synthesizeable RTL 

• Power management with multiple power domains, UPF, Power state tables. 

• High performance digital logic designs and integration SOC architecture, design flows and debug skills

• Hands on experience with FPGA emulation, silicon bring-up, characterization and debug 

• Working with multi-functional teams within Intel and external vendors across geographical boundaries to resolve architectural and implementation challenges with a focus on schedule 

• Modern design techniques and energy-efficient/low power logic design and power analysis 

• Power estimation (vector-less and vector-based), modeling, profiling, and post silicon power correlation 

• Computer architecture experience

• Bus fabric, including, but not limited to APB/AHB/AXI 

• Use of connectivity tools. 

• Key SoC design elements, arbiters, async FIFOs, DMAs, basic uControllers. 

• Asynchronous clock crossing means and methodologies 

• Bringing logic designs into high volume production 

• SoC Power Management RTL design using Verilog/System Verilog

• Design of Data path Power management flows Arbitration logic , Clock Domain Crossing and State Machines

• Multiple tape-outs experience reaching production with first pass silicon 

• Drive and improve digital design methodology to achieve high quality first silicon 

Preferred Qualifications that will make you stand out:

• Master's Degree with 4+ years of experience, or a PhD Degree with 2+ years experience and degree in Computer Engineering, Computer Science, Electrical Engineering or similar STEM degree

• Power intent UPF specifications knowledge

• Expertise with understanding of the power Management, reset, clock, and power domain challenges for large SoCs Experience with Design of Data path Power management flows

• Arbitration logic, Clock Domain Crossing and State Machines

• Knowledge of digital design involving multiple clock domains and power management

• Knowledge of low power design, tools, and methodologies

• Power intent UPF specifications knowledge a plus

• FE/RTL tools and design methodologies