SoC RTL Design Engineer

Job Description

Do Something Wonderful!

Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let’s do something wonderful together. Join us, because at Intel, we are building a better tomorrow.

As an SoC RTL Design Engineer the responsibilities will be, but not limited to:

• Develop the logic design, register transfer level (RTL) coding, and simulation for an SoC design and integrate logic of IP blocks and subsystems into a full chip SoC or discrete component design.

• Participate in the definition of architecture and microarchitecture features of the block being designed.

• Perform quality checks in various logic design aspects ranging from RTL to timing/power convergence.

• Apply various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.

• Review the verification plan and implementation to ensure design features are verified correctly and resolves and implement corrective measures for failing RTL tests to ensure correctness of features.

• Follow secure development practices to address the security threat model and security objects within the design.

• Work with IP providers to integrate and validate IPs at the SoC level.

• Drive quality assurance compliance for smooth IPSoC handoff.

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:
Bachelor's Degree in Computer Engineering, Computer Science, Electrical Engineering or similar STEM degree with 6+ years of industry experience in three or more of the following:

• Lint tools, CDC and RDC tools, timing constraints, fishtail.

• Experience with Verilog and system Verilog, synthesizeable RTL

• Power management with multiple power domains, UPF, Power state tables.

• High performance digital logic designs and integration SOC architecture, design flows and debug skills

• Hands on experience with FPGA emulation, silicon bring-up, characterization and debug

• Working with multi-functional teams and external vendors across geographical boundaries to resolve architectural and implementation challenges with a focus on schedule

• Modern design techniques and energy-efficient/low power logic design and power analysis

• Power estimation (vector-less and vector-based), modeling, profiling, and post silicon power correlation

• Computer architecture experience

• Bus fabric, including, but not limited to APB/AHB/AXI

• Use of connectivity tools.

• Key SoC design elements, arbiters, async FIFOs, DMAs, basic uControllers.

• Asynchronous clock crossing means and methodologies

• Bringing logic designs into high volume production

• SoC Power Management RTL design using Verilog/System Verilog

• Design of Data path Power management flows Arbitration logic , Clock Domain Crossing and State Machines

• Multiple tape-outs experience reaching production with first pass silicon

• Drive and improve digital design methodology to achieve high quality first silicon

Preferred Qualifications that will make you stand out:

• Master's Degree with 4+ years of experience, or a PhD Degree with 2+ years experience and degree in Computer Engineering, Computer Science, Electrical Engineering or similar STEM degree

• Power intent UPF specifications knowledge

• Expertise with understanding of the power Management, reset, clock, and power domain challenges for large SoCs Experience with Design of Data path Power management flows

• Arbitration logic, Clock Domain Crossing and State Machines

• Knowledge of digital design involving multiple clock domains and power management

• Knowledge of low power design, tools, and methodologies

• Power intent UPF specifications knowledge a plus

• FE/RTL tools and design methodologies

Inside this Business Group

The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

Other Locations

US, Santa Clara

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.



Annual Salary Range for jobs which could be performed in US, California: $144,501.00-$217,311.00
*Salary range dependent on a number of factors including location and experience

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.