AI Connectivity Performance Architect

Job Description

The NCCG group develops high-speed, cutting-edge Smart NICs (IPU) for Cloud customers with support for Crypto and Compression capabilities, advanced HW-based storage protocols, and compute capabilities. Our products are targeted for the comms and cloud data center industry and serve as a critical ingredient of Intel's Data-Centric strategy, shaping the Data Center and delivering an Intel end-to-end solution for this growing market. The IPU group is developing ASIC chips with and in-house SoC capabilities – from IP Design and verification through DFX and physical Design, to provide the full SoC capabilities for Smart NIC products.

For this Role we are looking for evelops end-to-end architecture performance models and including development of the target architecture state in silicon domain subsystem. Drives innovative technologies development for domain subsystems such as caches, IO, transport layer and network subsystems. Influences industry standards and supports ecosystem enabling and customers during architecture definition. Invents, conceptualizes, and specifies microarchitecture and architectural features for future generations or products to deliver optimized subsystems for AI connectivity products. Develops tests, test plans, and testing infrastructure for new architectures/features for subsystems, performs performance modeling simulations, and conducts analysis of test results using advanced statistics and data predictions for benchmarking performance and determining areas for improvement. Applies knowledge of domain technologies and translates domain requirements into blueprints for business process, data, infrastructure, applications, or platforms to be configured or created. Collaborates with cross functional teams (including driver and firmware) and defines software configuration control requirement for the technology domain.

Qualifications

Qualifications:

• 10 years of hands-on experience high speed networking semiconductor design and architecture, spanning stateful protocol processing, and Datapath traffic management.
• Design of cache subsystems, I/O interfaces PCIe, RDMA transport layer including ROCE, performance modeling with micro-architecture and RTL level fidelity, and hardware/software interaction. Hands-on operation of DV environments, creation of test plans, and results analysis. Ability to lead and manage other performance engineers and DV engineers. Thorough specification generation ability for device functionality at Arch, micro arch, and performance model level.

Preferred Qualifications:

• In depth knowledge of IBTA specifications (LWG) and its implementations.
• Accelerated system familiarity including CPUs, GPUs, custom ML accelerators.
• Proven ability to develop working silicon with predictable schedule
• Effective at internal and external facing interactions

Inside this Business Group

The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.

Position of Trust
This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.