Analog Circuit Design Engineer

Job Description

Intel is shaping the future of technology to help create a better future for the entire world. Our work in pushing forward fields like AI, analytics, and cloud-to-edge technology is at the heart of countless innovations. With a career at Intel, you'll have the opportunity to use technology to power major breakthroughs and create enhancements that improve our everyday quality of life. Join us and help make the future more wonderful for everyone. Want to learn more? Visit our YouTube Channel or the links below.

Life at Intel

Diversity at Intel

This role is within Intel’s Client Computing Group.CCG is a computing paradigm where services and data reside in scalable data centers, and those services and data can be accessed by any connected device over the Internet. Responsible for designing and optimizing processors, chipsets and other hardware for consumer devices while also working on the software ecosystem, including drivers and utilities that enhance user experience.

The Analog Circuit Engineer designs, develops, and builds analog circuits in advanced process nodes for analog and mixed signal IPs. Designs floorplans, performs circuit design, extracts chip parameters, and simulates analog behavior models. Creates test plans to verify design according to circuit and block microarchitecture specifications and evaluates test results. Verifies functionality to optimize circuit for power, performance, area, timing, and yield goals. Collaborates cross functionally to report design progress and collects, tracks, and resolves any performance and circuit design issues. Optimizes performance, power, area, and reduces leakage of circuits. Works with architecture and layout team to design circuit for best functionality, robustness, and electrical capabilities.

The engineer should possess the following behavior attributes:

·Ability to create and drive concepts to innovative solutions.

·Clear and effective technical communication, both verbal and written.

·Analytical and problem-solving skills.

·Effective team player with continuous learning mindset.

Qualifications

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

What we need to see (Minimum Qualifications):

• Bachelor’s degree in electrical engineering, Electronics Engineering or similar discipline with 3+ years relevant experience OR master’s degree in electrical engineering, Computer Engineering or similar discipline with 2+ years relevant experience OR Ph.D. in Electrical Engineering, Computer Engineering or similar discipline with 1+ years relevant experience.
• 3+ years' experience in designing/developing/building analog circuits in advanced process nodes for analog and mixed signal IPs, also in verifying functionality to optimize circuit for power, performance, area, timing, and yield goals. ( may be a combination of education, internship, and work experience)

Preferred Qualifications:

• PhD. in Electrical Engineering, Computer Engineering or similar discipline with 3+ years relevant experience.
• Exposure to device physics, power delivery, power integrity domain.Experience with simulation tools such as Cadence ADE/Synopsys Primewave, behavior model simulation tool such as VCS/NC-verilog, experience with layout tool such as Cadence Virtuoso

Overall experience should include

• Design, floorplan, perform circuit design, extract chip parameters and simulate analog behavior models
• Optimizes performance, power, area, and reduces leakage of circuits. Works with architecture and layout team to design circuit for best functionality, robustness, and electrical capabilities

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.Benefits at Intel

Our total rewards package goes above and beyond just a paycheck. Whether you're looking to build your career, improve your health, or protect your wealth, we offer generous benefits to help you achieve your goals. Go to Intel Benefits | Intel Careers for details of benefits available to you. Intel reserves the right to modify, change or discontinue benefit plans at any time in its sole discretion.

Inside this Business Group

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations.  DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Other Locations

US, OR, Hillsboro; US, CA, San Jose

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.Annual Salary Range for jobs which could be performed in the US $139,710.00-$197,230.00*Salary range dependent on a number of factors including location and experience

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.