SOC RTL Design Engineer Lead

In Q4 2023, Intel announced Altera will be reported as a separate business unit beginning on January 1, 2024, with ongoing support from Intel.

This position is associated to that standalone business strategy and is expected to fully transition to a standalone company at some time in the future.

Join Our Team: Altera has been delivering industry leading custom logic solutions to customers since inventing the world's first programmable logic device in 1984. The mission of Altera is to drive the future for FPGA technology/solutions around the globe. Within Altera, you'll be surrounded by some of the brightest minds/engineers in the world. Altera has the best-in-market FPGA with 2X better fabric performance per watt over the competition. These devices leverage heterogeneous 3D system-in-package technology along with the leading-edge process technologies which will ensure our continued market leadership. Altera is committed to aggressively expand our position for a broad range of market segments. Altera products have widevariety uses covering industrial automation, space exploration, data centers, automotive, and internet routers to name a few.

Job Description: We are seeking a skilled SoC Logic Design Engineer to join our team. The successful candidate will be responsible for developing the logic design, register transfer level (RTL) coding, and simulation for SoC designs. This role involves integrating logic of IP blocks and subsystems into a full chip SoC or discrete component design.

Key responsibilities include:

• Develops the logic design, register transfer level (RTL) coding, and simulation for an SoC design

• Integrates logic of IP blocks and subsystems into a full chip SoC or discrete component design

• Participates in the definition of architecture and microarchitecture features of the block being designed

• Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence

• Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation

• Reviews the verification plan and implementation to ensure design features are verified correctly

• Resolves and implements corrective measures for failing RTL tests to ensure correctness of features

• Follows secure development practices to address the security threat model and security objects within the design

• Works with IP providers to integrate and validate IPs at the SoC level

• Drives quality assurance compliance for smooth IP/SoC handoff

• Excellent communication and documentation skills

• Mentoring team members

You must possess the below minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Requirements:

• Bachelor's degree with 9+ years of experience, or Master's degree with 6+ years of experience, or PhD with 4+ years of experience in eitherElectrical or Computer Engineering, Computer Science, Math, Physics, or STEM-related field. 

• 9+ years of experience in RTL and System Verilog.

• In-depth experience with hardware design, including logic design, state machines, control units, processor sub-systems, and network on chips.

• In-depth knowledge of industry-standard tools and flows for front-end design, including synthesis, STA, Spyglass-based checks, and power domains.

Preferred Qualifications:

• Experience with AES/SHA, as well as compression and decompression algorithms

• Knowledge of Network on Chips and Control Processors

• Experience in programming languages such as Python