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Senior Analog Engineer

Toronto, Ontario, Kanada Anzeigen-ID JR0260900 Stellenkategorie Silicon Hardware Engineering Arbeitsmodus Hybrid Erfahrungsstufe Experienced
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Job Description


Do Something Wonderful!

Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let’s do something wonderful together. Join us, because at Intel, we are building a better tomorrow. Want to learn more? Visit our YouTube Channel or the links below!

·      Life at Intel

·      Diversity at Intel

Intel is shaping the future of technology to help create a better future for the entire world. Our work in pushing forward fields like AI, analytics, and cloud-to-edge technology is at the heart of countless innovations. With a career at Intel, you'll have the opportunity to use technology to power major breakthroughs and create enhancements that improve our everyday quality of life. Join us and help make the future more wonderful for everyone.

The Intel Toronto office is dedicated to designing SerDes IP for use by customers that require flexible protocol support in addition to best-in-class performance and power. We have a long track record of silicon success over multiple technology nodes.

We are looking for the right person to take an Analog Design role in the design and analysis of analog circuits - someone who will seize the opportunity to lead, design, and validate foundational analog IP such as Voltage Regulators and References, High Voltage Circuit Design such as level shifters, charge pumps, and bias circuits, PLLs, CTLE/DFE sub-blocks for TX and RX circuits, registers, data converters, etc.

The key responsibilities of this person include the following:

  • Designing, developing, modifying and evaluate complex analog and mixed-signal electronic integrated circuitry.
  • Determining creative design approaches and parameters.
  • Designing complex circuit blocks with best-in-class power, performance, and area.
  • Characterize this circuitry in the lab using test chip and product silicon.
  • Creating detailed documentation to enable co-ordination between analog, layout, digital, system, and lab teams as well as customer teams.
  • Providing schedule estimates for work on circuits blocks to enable project planning.
  • Maintain familiarity with SerDes circuit design literature.

The Analog Engineer should possess the following attributes:

  • Excellent communication: Expected to drive clarity across partners, managers.
  • Excellent teamwork: With a relatively small team, we need everyone to help however and wherever they can.
  • Willingness to mentor and guide team on industry standard best practices.

Qualifications


You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

What we need to see (Minimum Qualifications):

  • Bachelor's degree in Electrical Engineering, Computer Engineering or related technical field with 3+ years experience OR a Master's degree in in Electrical Engineering, Computer Engineering or related technical field and 2+ years of related experience OR a PhD in Electrical Engineering, Computer Engineering or related technical field.
  • Experience Cadence schematic and layout tool suite and Spice/FastSpice/AMS simulation tools.
  • Experience with circuit design, layout, circuit reliability tools/methodologies.
  • Experience with design model building and validation methodologies.

How to Stand out (Preferred Qualifications):

  • 2+ years of experience in design of high performance PLL (LC, VCO, low power, low jitter).
  • 1+ years of experience in design and validation of fractional dividers.
  • 1+ years of experience in advanced LC Tank components layout techniques.
  • 1+ years of experience in PLL Matlab and Phase Noise modeling.
  • 1+ years of hands-on experience in Lab post-Si validation and characterization.
  • Knowledge of VerilogA for analog behavioral modeling, TCL, Perl, C, python or other scripting languages.

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.


Inside this Business Group


IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.


Posting Statement


All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits


We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.


Intel is committed to a culture of accessibility. Intel provides accommodations to applicants and employees with disabilities. Find information and request accommodation here.


Annual Salary Range for jobs which could be performed in Canada:CAD 126,420.00-189,480.00
Salary range dependent on a number of factors including location and experience


Working Model


This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
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