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Design for Test (DFT) Engineer

Fort Collins, Colorado, USA| Austin, Texas, USA| Phoenix, Arizona, USA| Santa Clara, Kalifornien, USA Anzeigen-ID JR0259682 Stellenkategorie Silicon Hardware Engineering Arbeitsmodus Hybrid Erfahrungsstufe Experienced Arbeitszeitmodell Vollzeit

Job Description

Role and Responsibilities:

The world is transforming - and so is Intel. Here at Intel, we believe the world needs technology that can enrich the lives of every person on earth. We work every single day to design and manufacture silicon products that empower people's digital lives. Do you love to solve technical challenges that no one has solved yet? Do you enjoy working with cross functional teams to deliver solutions for products that impact customers lives? If so, Come join us to do something wonderful.

Responsibilities for this DFT Engineer will include but are not limited to:

  • Develops the logic design, register transfer level (RTL) coding, simulation, and provides DFT timing closure support as well as test content generation and delivery to manufacturing for various DFx content (including SCAN, MBIST, and BSCAN).
  • Participates and collaborates in the definition of architecture and microarchitecture features of the block, subsystem, and SoC under DFT being designed (including TAP, SCAN, MBIST, BSCAN, proc monitors, in system test/BIST).
  • Develops HVM content for rapid bring up and ramp to production on the automatic test equipment (ATE).
  • Applies various strategies, tools, and methods to write and generate RTL and structural code to integrate DFT.
  • Optimizes logic to qualify the design to meet power, performance, area, timing, test coverage, DPM, and test time/vector memory reduction goals as well as design integrity for physical implementation.
  • Reviews the verification plan and drives verification of the DFT design to achieve desired architecture and microarchitecture specifications.
  • Ensures design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
  • Integrates DFT blocks into functional IP and SoC and supports SoC customers to ensure high quality integration of the IP block.
  • Collaborates with post-silicon and manufacturing team to verify the feature on silicon, support debug requirements, and document all learnings and improvements requirement in design and validation.
  • Drives high test coverage through structural and specific IP tests to achieve the quality and DPM objectives of the product and develops HVM content for rapid bring up and production on the ATE.

The ideal candidate should exhibit behavioral traits that indicate:

  • Excellent interpersonal skills, including written, verbal, and presentation communications.
  • Attention to detail and organizational skills.
  • Ability to build and manage effective relationships with team members, peers, and customers.
  • Tolerance of an ambiguous environment with high motivation and results orientation.


You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Possess a Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field and 6+ years' experience OR MS degree in Electrical Engineering, Computer Engineering, or a related field and 4+ years' experience.

  • At least one of the key DFT features such as TAP/JTAG, Scan/ATPG or Array DFT (MBIST/PBIST) (This is a key skill requirement.)
  • SoC IP DFT, design integration or verification.
  • EDA tools such as ATPG tools, Siemens Tessent shell, VCS simulation and/or debug tools.

Preferred Qualifications:

  • DFT microarchitecture experience.
  • Silicon enabling debug or test pattern development experience.
  • Design automation skills and proficiency in programming or scripting languages.
  • Structural design flows, including timing, routing, placement or clocking analysis.
  • High volume manufacturing requirements and test flows.
  • Ideal candidate is a self-starter, can organize complex issues and drive them to closure.
  • Can multitask and prioritize.
  • Mentor and lead junior engineers.

Requirements listed could be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Inside this Business Group

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations.  DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Other Locations

US, TX, Austin; US, AZ, Phoenix; US, CA, Santa Clara

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.


We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.

Annual Salary Range for jobs which could be performed in US, Colorado, California: $144,501.00-$217,311.00
*Salary range dependent on a number of factors including location and experience

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.

Posting End Date

The application window for this job posting is expected to end by 06/27/2024

Maggie, Offensive Security Researcher

Maggie Offensive Security Researcher

Ich wollte schon immer etwas tun, das die Welt verändert – bei Intel fühle ich mich geschätzt und ich habe mehr Selbstvertrauen gewonnen. Die Arbeit gibt mir das Gefühl, dass ich in der Lage bin, Großes zu leisten.
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