Lead Product Development Engineer, Analog Test Engineer

Job Description

• Experience of handling team of 4 or more.
• Drives and develops testability and manufacturability of integrated circuits from the component feasibility stage through production ramp.
• Contributes to design, development, and validation of testability circuits, test flows, and methodologies for new products through evaluation, development, and debug of complex test methods. Interfaces with process development, fab, factory, assembly, quality and reliability, and manufacturing groups to enable post silicon HVM ramp.
• Evaluates new designs on automatic test equipment (ATE) and works with the design, DFx, and product development teams to debug functionality and performance issues to root cause.
• Performs ATE device characterization, utilizes that data to define datasheet specifications and performs yield analysis.
• Collaborates with designers to drive design for test/debug/manufacturing (DFT/DFD/DFM) features enabling efficient production testing of new products
• Develops and debugs complex software programs to convert design validation (DV) vectors and drive complex test equipment. Creates and tests validation and production test hardware solutions.
• Works with the design and/or product development team to perform ATE to DV correlation, debug functionality and performance issues, perform circuit characterization, and design spec validation.
• Ensures manufacturability over process and product design through thorough analysis of process and spec corners and works with design to resolve yield issues before manufacturing ramp. Drives test time reduction through analysis of fallout data versus test time for various IPs to balance and drive overall product cost optimizations.
• Analyzes early customer returns with emphasis on driving test hole closure activities.
• Tests and characterizes for DC, power and thermals, including thermal profiling and recipe tuning for production thermal control. Provides tailored trimming and calibration for power delivery and/or thermal sensing circuits to each individual die and provides building blocks for power and performance binning and improvement.
• Works with fab, assembly, and test factory partners and planners to support production ramp.
• Reviews test plans with design, conversion of pre silicon content to patterns, and additional content development as needed, reviews HVM data with design to identify and root cause the issues.
• May also manage execution of new product introductions in the fab, fab process targeting, product/process optimizations, and participate in factory task forces to bring product perspective and respond to product issues. Optimizes product supply through data analysis of post silicon bin split, die level cherry pick (DLCP), and optimize sort/test content and yield downstream through data analysis.

Qualifications

Job Qualifications:

In this position, you will be responsible for Test vector/content implementation and validation of various DFT features such as Analog DFX like loopback , RTERM leakage ,JTAG , BScan as well as Memory IO DFX, Combphy ,Display , PCIE gen4/5 , USB3  etc. for Intel's leading edge SoC designs. Analog IP  testing will be majority of the work.

• Working with pre-Si design/DFT teams to provide feedback and ensuring vectors are meeting ATE requirements.
• Stabilizing vectors/content from Si bring up to volume production, meet DPM requirements and test cost requirements on ATE.
• Delivering best in class product impacting Intel's bottom line.
• Proven Experience in Design for Test/Debug logic design/implementation of Large SOCs
• Expertise in various Analog IP like PCIe gen4/5 ; DMI ; USB3/3.1 ; SATA ; memory test, algorithms, Boundary scan and JTAG.
• Good experience in micro-architecture, RTL coding, system Verilog, test bench development Knowledge of other ad-hoc DFT tests, on chip interconnect buses.
• Experience with Synopsys and/or mentor tools and basic understanding of the SoC development flow is must.
• Expertise in Si debug, shmoo analysis, statistical analysis to meet DPM and Test Cost targets.
• Knowledge of scripting in Perl, shell, Python.

Qualification:

• Candidate should possess a Bachelors or master's degree in computer/ electrical/Electronic Engineering with about 12+ years of experience.
• Strong knowledge of DFT architecture, design, methodologies and tools - Analog DFT, Analog IPs, JTAG, etc. Good understanding of Test Engineering and tester debug is desirable.
• Experience with DV (Analog validation on RVP/MDV boards) enabling and bebug.
• Hands on design/validation experience with strong/proven debug skills.
• A very good team player with good interpersonal, planning, and excellent communication skills.

Inside this Business Group

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations.  DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.


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Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.