3DIC Extraction QA Engineer

Job Description

Deliver industry standard parasitic extraction tools / flows and capabilities for Intel's Customers. Primary responsibility includes but not limited to enablement of PDK Custom and ASIC extraction flows/ methodologies and test the PDK collaterals. Job function includes assuring the quality of Extraction decks by setting up various flows/methodologies. Should be self-driven and able to take up new tasks. Should closely interact with EDA vendors Synopsys, Cadence, Siemens, Redhawk SC and ungate the issues in convergence of 3D Stacked Dies for enablement of new features / additions to the existing flows / methodologies. Provide support for internal customers, collaborate with EDA vendors for enhancement of the flows based on customer requests. Should be proficient in documenting the observations made from the flows executed. Automation of the key capabilities for design productivity is add-on responsibility. Candidate should validate extraction on test cases provided for both Single and Multi Die configurations using TSV and Bumps collaterals and also contribute in defining Extraction Methodology for 3DIC domain. Candidate should have good hands on exposure on automation using TCL, Perl, Python and good understanding of 3DIC/low power/high speed ASIC PNR flows, Layout Verification and Timing Signoff methodologies.

Qualifications

7+ Years of experience in Extraction, PNR/APR domains with MTech/BTech degree. Must have worked on industry standard tools for extraction, like Star-RC / QRC, Cadence Innovus / Synopsys ICC2 tools with relative design experience. Candidate should have exposure to a breadth of EDA tools from different vendors Synopsys, Cadence, Siemens, Redhawk SC. Candidate should have excellent interpersonal, analytical, written, and verbal communication skills; strong team player. Candidate should have in-depth knowledge of the 3DIC Design requirements, ASIC technology files, ASIC RTL2GDSII flow development and QA.

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.


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Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.