Senior Emulation Engineer

Job Description

• Builds emulation and FPGA models and solutions from RTL design using synthesis, partitioning, and routing tools.

• Develops, integrates, tests, and debugs hardware and software collateral in simulation, emulation, and FPGA models for testing new features, writes directed tests, develops the test environment and hybrid emulation environment, and supports verification of hardware and software/firmware.

• Defines and develops new capabilities and tools to achieve better verification through improved emulation and FPGA model usability.

• Enables acceleration of RTL development and improve emulation/FPGA model usability for pre-silicon verification, post silicon validation, and software development.

• Develops improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform and interfaces with and provides guidance to verification teams for optimizing pre-silicon verification environments, test suites, and methodologies for emulation efficiency.

• Develops and utilizes automation aids, flows, and scripts in support of emulation utilization.

• Applies understanding of emulation and FPGA prototyping tools and methodologies, SoC integration, emulation transactors, emulation performance and optimization techniques, RTL simulation, and hybrid emulation environments (virtual platform and FPGA/emulation model).

• Collaborates with design, power and performance, silicon validation, and software teams, and participates in SoC and IP bring up, root causes testbench issues, IP and SoC testcases, and emulator/FPGA environment issues.

Qualifications

• Applicants must possess a Bachelor or higher of Science degree in Electronics Engineering, Computer Engineering or equivalent with at least 5-7 years of relevant work experience. We're looking for candidates with the following attributes.

• Excellent problem-solving skills and a self-starter.

•  Highly motivated to learn and adapt to fast changing technologies and environments.

•  Effective communication and collaboration skills.

•  Ability to work effectively in a cross-site team environment.

•  Demonstrate fundamental values such as accountability, integrity, and a winning mindset.

Minimum qualifications include any of the following:

• Computer architecture, logic verification with a good understanding of logic design concepts.

• Verilog, System Verilog.

• RTL simulation and test bench development experience.

• FPGA synthesis, place, and route tools.

• Software programming skills, proficient in C and/or C++, familiar with Linux based development environments, tools, and scripting languages such as Python, Perl, TCL/TK, and good software engineering practices.

Inside this Business Group

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations.  DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.