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Analog Layout Design Engineer

Hajfa, Hajfa, Izrael| Jerozolima, Jerusalem, Izrael| Petaẖ Tiqwa, Central District, Izrael Identyfikator oferty JR0262470 Kategoria Silicon Hardware Engineering Tryb pracy Hybrydowy Poziom doświadczenia Doświadczony Wymiar etatu Praca na pełny etat

Job Description

SIPGPDE (Server/IP Design Team) is looking for an Analog Layout Design Engineer to join our team, developing the industry's best high speed communication devices. Take part in our design innovation chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

Your responsibilities will include, but not limited to:

  • Designing Layout of sensitive analog components such as receivers, transmitters, clocking, ADC/DAC, PLL, and LDO for High-Speed IO IPs using TSMCs & INTEL's current and next-generation process nodes.
  • Working with complex analog signal circuits for a given design specification following design verification tools for process design rules, electron migration, voltage drop (IR), ESD, and other reliability checks on the layouts.
  • A Layout Designer role: you need to align with Design constraints, Floorplan, Power grid, ESD, Bumps, reliability in order to meet performance, and all required verification, following a detailed block plan to align with project schedule.
  • Troubleshoots a wide variety of topics including difficult design issues.


  • B.Sc. in Electrical Engineering or Physics.
  • At least 5 years of experience in Analog Layout Design/Physical Design.
  • Expansive Layout knowledge and practical application of methodologies and physical design.
  • Excellent communication and expected to drive clarity across customers, stakeholders, partners, and managers.
  • Excellent teamwork and being flexible in assignments as per project needs.
  • Previous experience in high-speed SERDES/Ethernet - Advantage.

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.


We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
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