Job Description As DFT engineer, candidate is responsible for Design for Manufacturing and Testability of our products. Responsibilities include design & verification using: Scan ATPG tools for pattern generation and coverage debug, Gate Level Simulation for running these patterns through VCS simulations, Array DFT MBIST or LBIST for array testing, TAP for controlling and debug the design, and more.
Key Qualifications-The candidate should possess a B.Sc or M.Sc in Computer or Electrical Engineering with 5+ years of DFT experience.-Knowledge of Verilog and/or VHDL. Experience with simulators and waveform debugging tools.-Excellent understanding of various DFx tools.-Experience using an interpretive language such as Perl, Python or Ruby.EducationMS or BS Degree in technical discipline
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.