Job Description Summary • BSEE/MSEE/PhD, with 5-8 years of digital design experience. • Familiarity or experience in RTL design with Verilog and/or VHDL is required. • Familiarity or experience with RTL verification and timing analysis/closure on Linux/UNIX platforms is a strong plus. • Knowledge of high speed serial system interfaces (such as Ethernet, IEEE 1588, CPRI or Serial Rapid IO) is a strong plus. • Familiarity with Perl, C++, Java and shell scripts is a plus.