Senior Physical Design Engineer

Job Description

Do Something Wonderful!

Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let’s do something wonderful together. Join us, because at Intel, we are building a better tomorrow. Want to learn more? Visit our YouTube Channel or the links below!

• Life at Intel
• Diversity at Intel

The Network and Edge group (NEX) at Intel drives the software-defined transformation of the world's infrastructure - in data centers, in networks, and at the edge. We are a team of problem solvers, experimenters, and innovators who are dedicated to designing the network technologies that currently lead and continue to transform data-center and AI ecosystems.

Intel's Network Silicon Solutions team is looking for a designer to develop one of Intel's flagship Networking and Edge products.

You will be responsible for, but not limited to:

• Designing a full chip top-level floorplan, pushdown to blocks, then reassembly and signoff across all of the normal domains.
• Making contributions towards the physical design system and physical implementation like floorplanning, power grid insertion, placement, CTS, route.
• Troubleshooting a wide variety of physical design complex issues and apply proactive intervention.
• Working closely with RTL teams, DFT teams, and EDA tool vendors.

The Senior Physical Design Engineer should possess the following behavioral traits.

• Excellent teamwork skills including ability to work with multiple and remote groups worldwide.
• Motivated self-starter, with strong ability to work independently as well as in a team environment.
• Strong verbal and written communication skills in English.
• Flexibility and maturity in facing uncertainties and changing priorities/responsibilities.
• Act with velocity and a strong sense of urgency.
• Respect cultural diversity and sensitivity.
• Agility in learning, improving, and innovating.

Qualifications

What we need to see (Minimum Qualifications):

• Master's degree in electrical or computer engineering with 7+ years of industry experience or bachelor's degree with 9+ years of industry experience.
• 5+ years' experience with physical design tools and methodologies in sub-micron technology, including Place and Route (i.e. ICC2 / Fusion Compiler) with physical verification knowledge (i.e. DRC/LVS/Antenna).
• 5+ years' experience with Tcl, Perl, or Python coding skills to automate design process and improve efficiency in EDA tool suites.

How to Stand out (Preferred Qualifications):

• Master's degree in electrical or computer engineering with 12+ years of industry experience or bachelor's degree with 15+ years of industry experience.
• 10+ years of experience in one or more the following:
  • Static timing analysis (PrimeTime), Electromigration (EM), IR-Drop, Xtalk analysis (PT-SI). Design rule checking (DRC), layout versus schematic (LVS), and Antenna checks, and familiarity with industry-standard verification decks and rule sets.
  • Formal equivalence verification experience (Synopsys Formality or Cadence LEC).

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Amazing Benefits!

Here at Intel, we invest in our people. Beyond health, dental, and retirement benefits, Intel’s benefits package includes 14 paid holidays per calendar year, three weeks of paid vacation, and four-week paid sabbatical every four years of employment.  Intel also offers employees five bonuses per year dependent on overall company and personal performance, and an employee stock purchase program. Find more information about our Amazing Benefits here: https://jobs.intel.com/benefits

Inside this Business Group

The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers.

Other Locations

US, OR, Hillsboro; US, PA, Allentown; US, CA, Folsom; US, MA, Hudson

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.



Annual Salary Range for jobs which could be performed in US, California: $162,041.00-$259,425.00
*Salary range dependent on a number of factors including location and experience

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.