Process TD Frame Cellset Engineer

Job Description

Logic Technology Division (LTD) Frame Cellset Owner (FCO) team is looking for an individual responsible for the integration of scribeline cells (fab process monitors, litho alignment marks, litho metrology, electrical test, etc.) into frame layouts which accompany each product to support fabrication. The Frame Cellset Owner team works closely with many organizations including Process Technology Development, Product Design, Litho Resolution Enhancement Techniques, Design Enablement Runsets, Intel Tapeout Operations, Intel Mask Operations, and the Virtual Factory to enable all Intel process technologies both during development and continuing through high volume manufacturing. The Frame Cellset Owner team is responsible for the accuracy of all frame-related collaterals released. The primary responsibilities may include (but are not limited to): - Performing layout edits based on process design specifications and fab module owner guidelines. - Dispositioning drawn data changes through XORs and/or design rule flows. - Providing frame dimension and field configuration estimates to product design teams. - Verifying the placement of the scribeline cells in the frame to meet fab process module BKMs as well as technology design specifications. - Ensuring proper frame data output and validating the integrity of the frame through the tapeout process. - Documenting and communicating frame revision changes and NPI setup data to manufacturing organizations through the Graphics website. People with the following behavioral traits: - Analytical and problem-solving skills - Organized, with attention to detail and quality - Ability to work effectively with a team - Precise communication skills - Flexible to multitask and work with minimal supervision.

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes and project work, internships, military training, and/or work experience.

Minimum Qualifications:

• Candidate must possess a Master's or Ph.D. degree in Electrical Engineering, Chemical Engineering, Materials Science, Industrial/Mechanical Engineering or other related field of study.
• 5+ years of semiconductor manufacturing experience.

Preferred Qualifications:

1+ years of experience in one or more of the following:

• CAD layout tools, desirable are familiarity with Cadence Virtuoso and Calibre design software
• Design flow UNIX computing environments, and basic shell programming.
• Experience in semiconductor manufacturing process flow, including lithography and metrology.

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.