DFT Engineer

Job Description

The Graphics hardware IP team , within the CGAI (Client Compute Group and AI), is responsible for design and development of Graphics, Media and Display IPs as well as discrete Graphics SoCs (GPUs), targeting both Client Device and Datacenter markets. The XSE organization is at the center of Intel's push into the discrete Graphics SoCs (ARC GPUs) market segment targeting next-generation applications such as High-performance computing, Deep learning / training, Cloud Graphics, Media analytics, High-end gaming. In this position you will be part of a world class DFT team which works on next generation SOCs and IPs. You will be working with a group of highly talented engineers working on cutting edge technologies. Candidate will be responsible for DFT design, RTL coding, DFT verification, Array and logic test development, test vector generation and simulation validation, vector bringup on silicon and post-silicon debug. Candidate will be working closely with microarchitects, function design, validation and back-end teams to ensure correct by construct DFT. Post silicon test engineering teams to ensure quick bringup of DFT vectors and help the team through to production. You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through relevant schoolwork, internships, jobs and/or research experience.

Qualifications

Minimum skills and Experience: Bachelors in Electrical/Computer Engineering or related field with 1+ years of academic or industry experience. Or a Masters in the same fields with 3+ months of academic or industry experience. Your experience should be in the following Experience with ASIC design flow (SoC/IP design, integration, or verification) Design automation skills and/or proficiency in programming or scripting languages Preferred Skills and Experience At least one of the key DFT features such as TAP/JTAG, Scan/ATPG or Array DFT (MBIST/PBIST) Exposure to EDA tools such as ATPG tools, Mentor Tessent shell, Synopsis VCS simulation and/or debug tools Awareness of Structural design flows, including timing, routing, placement or clocking analysis

Inside this Business Group

The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.


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Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.