Design Quality and Reliability Engineer

Job Description

In this position you will work in a group of pre-Silicon design Quality and ReliabilityEngineers (QRE), supporting development of CPU and Hard IPs on the most advanced Intel processes. You will be responsible for pre-Silicon verification and execution of simulations in the design phase as well as developing new design methods, flows and tools for VLSI circuit IP and SoC projects.Primary responsibilities are to establish technical leadership within a team of engineers and lead the overall partnership with Hard IP and SoC design teams. Other responsibilities include performing quality audits in the design phase, risk assessments on pre-silicon design reliability and analysis of physical design performance verification (PV) as well as reliability verification (RV) results.Key tasks include pre-silicon design modeling and correct-by-construction design simulation verifications to mitigate circuit marginalities in Device Aging, Interconnect Reliability (Electromigration), Electro Static Discharge (ESD), Latch-Up (LU), Soft Error Reliability (SER) as well as design/package interactions. Other tasks include project management and technical guidance to junior team members. An important aspect of this role is to assess risks associated with design process marginalities and drive resolutions with partners from design architecture and manufacturing teams

Qualifications

Bachelors / Masters / PhD in Electronics Engineering, Physics or Material Science with 5 to 10 years of relevant experience in circuit simulation, PV, RV and Physical Design. Strong skills in device physics and circuit operations along with technical problem solving, communication and data analysis. Knowledge in analog and digital circuit design methodologies (timing, noise, physical design, circuit design, mask design and layout). Understanding of optimizations and trade-offs to achieve better performance, power, reliability. Experiences in overall VLSI design flow, technology development and device physics are a plus. Design knowledge in the areas of device aging, Interconnect Reliability and ESD-LU is a plus. Experience in programming using scripting languages such as Python Perl or VB is a plus. Excellent communication and presentation skills. Good written and spoken English. Ability to effectively work in a team environment. Well organized, with the ability to effectively manage multiple tasks.

Inside this Business Group

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations.  DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Other Locations

IN, Hyderabad

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.


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Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.