Analog Design Engineer - PDK Support

Job Description

At Intel, Design Enablement (DE) is one of the key pillars enabling Intel to deliver winning products in the marketplace. You will directly drive and work with DE cross functional teams to ensure design-kit leadership for customer enablement of cutting-edge technologies. You will work with customers to outline critical requirements, collaborate with Intel internal partners to define issue scope, plan execution, and innovate competitive solutions to meets customer needs.

This role is to support PDK for custom template design layout/integration validation, and for analog design impact analysis across all Intel leading edge PDKs.

With strong analog/custom design background, you will lead integration layout validation of custom template cells like MFC(Multi-Finger-Capacitor), BGdiode, resistor, or clamp to make sure integration guidelines to foundry customers are all clear and correct.

For impact analysis, you will collaborate with DE teams to outline industry standard analog FOM and relevant indicators, construct, maintain and generate the simulation results.

You will need to have deep understanding of analog design behind each indicator to interpret the gap between PDK to PDK.

You will conduct this analysis across all Intel leading advanced technology process nodes and support relevant documentation. Tasks also include owning/maintaining training documents, user guide, and customer issue/ticket support.

As a DEAS (Design Enablement Application and Support) key member, you must have good communication skills to interact with customers directly, apply analytical problem-solving capability to identify the key requests, and root-cause the issue in a teamwork environment with DE stakeholders to support and enable customer success.

Qualifications

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:
Candidate must possess a BS degree with 6+ years of experience or MS degree 4+ years of experience or PhD degree with 2+ years of experience in Electrical/Computer Engineering, or related STEM fields.
4+ years of experience in the following:
- Prior design ownership for analog IPs (for example, PLL, AADC, ADAC, PCIE, GPIO, DDR) or equivalent designs. Solid knowledge for foundation circuits/blocks for these IPs.
- Strong background in analog design background, and real product experience.
- Proficient in performing spice simulation, hspice or spectre, or equivalent simulators, and extract simulation results.
- Experienced in working with layout engineers to build tight matching, low capacitance, low power analog blocks, resistors, capacitors, high voltage devices, etc.
- Skilled in layout tools, like Cadence Virtuoso, Synopsys Custom Compiler, ICV, Calibre or equivalent tools.
- Intel and/or external foundry process technology knowledge in advance nodes.

Preferred Qualifications:
- Solid knowledge /experience in transistor level physics and simulation.
- Layout experience would be a good plus.
- Customer-oriented and self-motivated mindset.
- Good communication skills; both verbal and written.
- Proven ability to analyze issues, solve problems, and bring closure.

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.