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Design Methodology and Flow Development Engineer

Hsinchu, Taiwan, Taiwán| Taipéi, Taiwan, Taiwán ID de la oferta JR0257390 Categoría de Trabajo Silicon Hardware Engineering

Job Description

About the Group:

Intel Foundry Services (IFS) is an independent foundry business established to meet our customers' unique product needs. With the first "Open System Foundry" model in the world, our combined offerings of wafer fabrication, advanced process, and packaging technology, chiplet, software, robust ecosystem, and assembly and test capabilities help our customers build their innovative silicon designs and deliver full end-to-end customizable products from Intel's secure, resilient, and sustainable source of supply.

About the Role:

  • IFS Customer Design Enablement (CDE) team is a critical team to lead Intel's design methodology and flow in advanced technology. 

  • As a role in IFS CDE team, should be familiar with design flow and qualified to have design experience in one of following areas: ASIC, 3DIC, and Reliability designs.

  • In the position of ASIC design engineer, the candidate will be responsible for the ASIC design methodology/flow development especially in the areas of synthesis, floorplan, PnR, Timing, PDN, and ECO designs.

  • In the position of 3DIC design engineer, the candidate will be responsible for the 3DIC design methodology/flow development especially in the areas of system partition, system floorplan, I/O and Bump/TSV planning, and 3DIC integration designs.

  • In the position of reliability design engineer, the candidate will be responsible for the reliability design methodology/flow development especially in the areas of EM/IR, thermal, SI/PI designs.

  • As part of this role, the candidate is expected to work with various cross functional teams and external EDAs to oversee the execution all the way. 

  • The candidate is capable to run design flow, validate new design flow/methodology and responsible to figure out the potential flow issue. 

  • In addition to the above, the candidate's ability to come up with a design solution is a plus.

The selected candidate for the Design Methodology and Flow Development Engineerposition will be responsible for but not limited to:

  • Strong expertise in any one or multiple of the following areas:
  • Advanced ASIC (APR) design including Synthesis, Floorplan, PnR, PDN, Timing, and ECO
  • Advanced 3DIC design including system partition, system floorplan, I/O and Bump/TSV planning, and 3DIC integration
  • Advanced reliability design including EM/IR, thermal, SI/PI
  • Design flow development and EDA tool certification
  • Design Service
  • EDA design tool and design automation
  • Self-motivated and detail-oriented, capable of articulating complex concepts and solutions
  • Demonstrated design experiences to secure supports and working experiences with cross-functional teams in achieving goals

The ideal candidate should exhibit the following behavioral traits:

  • Coordination mindset with a focus on development design methodology and flow
  • Skills with EDS ecosystem partnership collaborations


You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and will be a factor in identifying top candidates.

Minimum Qualifications:

  • MS/Ph.D. degree in Electrical Engineering, Computer Science, or a related field of study
  • 3+ years experiences in design, flow development, and EDA enablement
  • Minimum 1+ years' experience in one of following areas: ASIC, 3DIC, reliability
  • Knowledge in digital IC design basics
  • Knowledge in semiconductor manufacturing, assembly, and packaging basics.
  • Technical background in EDA tools
  • Programming skill: TCL, Python

Preferred qualifications:

  • Experience in PDK development is a plus
  • Experience in 2.5D and/or 3D integration chip design
  • Evidence of organizational and planning skills for engineering projects
  • Good communication and presentation skills to executive project coordination
  • Experience working with multiple function teams for EDA ecosystem
  • Ability to set goals & objective with priorities, drive results across cross functional boundaries
  • Excellent project control skills to prioritize the urgencies to meet schedule in an ambiguous environment

Other Locations

TW, Taipei

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.


We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.

Maggie, Offensive Security Researcher

Maggie Offensive Security Researcher

Siempre he querido hacer algo que cambie el mundo. En Intel, me siento apreciada y he ganado más confianza en mí misma. Me hacen sentir que soy capaz de lograr grandes cosas.
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