Senior Director of EDA Engagement for Design Enablement

Job Description

About the Technology Development Group:

Technology Development (TD) is the heart and soul of Moore’s Law at Intel, enabling Intel to create world-changing technology that enriches the lives of every person on earth. TD’s more than 13,000 employees drive breakthrough research, develop next generation process and packaging technologies, while also running high volume manufacturing operations in its state-of-the-art facilities in Oregon and Arizona.

The Design Enablement (DE) team in TD works closely with the technology team to maximize the value proposition of the technology for our customers thru Design Technology Co-Optimization (DTCO) and delivers the Process Design Kits (PDKs) and Foundation IP (FIP) that designers need to support their product design work and fully leverage the technology.  The DE organization scope includes technology design rules & models, technology and IP testchips, Process Design Kits (PDKs) and Foundational IP.  The Foundational IP team is responsible for developing the essential building blocks for Intel’s advanced nodes.  This includes Digital, Memory, and GPIO/mixed-signal IP solutions.    FIP is the cornerstone of a Foundry’s technology offering.  It is essential for technology definition, yield development, and for achieving the best time-to-market for customers on a new technology node. 

About the Role:

In this role, you will direct the strategic Design Enablement technical engagements with EDA (Electronic Design Automation) suppliers.

Responsibilities include but are not limited to the following:

• Developing and driving a coherent Design Enablement EDA strategy to meet the needs of Process Design Kits and Design-Technology Co-optimization on next-generation process technology nodes.
• Serving as the central Design Enablement contact for both tactical and strategic EDA issues that require escalated attention from an EDA supplier.
• Planning and chairing regular executive review meetings between Intel Design Enablement and individual EDA suppliers.
• Identify agendas and concise key messages to achieve Design Enablement strategic directions through executive decisions.
• Track the performance of EDA suppliers to their commitments through rigorous indicators.
• Manage a small team of technical contributors to assist in the tracking of EDA related issues and indicators.

Experience Required:

• 8+ years of experience working with EDA tools and/or EDA suppliers in the context of semi-conductor design, EDA design automation activities; EDA development; etc.  
• 5+ years of experience technically contributing or leading in a design enablement area including: test-chip development; foundational IP creation; PDK development; process modeling; semi-conductor design
• Familiarity with the fundamental concepts associated with parasitic extraction, physical verification, auto place and route, circuit simulation, and reliability verification.
• Superb written and oral communication skills demonstrated through work experience including organizational leadership or program management.  
• Demonstrated ability to track and plan work in a disciplined fashion.
• Demonstrated ability to set a strategic direction for a technical organization.

Qualifications

• Bachelors, Masters or PhD degree in Electrical Engineering or Computer Engineering or related field.
• 8+ years of experience in process technology feature enablement with EDA vendors

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Other Locations

US, AZ, Phoenix; US, CA, Folsom; US, OR, Portland

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.



Annual Salary Range for jobs which could be performed in US, California: $225,662.00-$361,046.00
*Salary range dependent on a number of factors including location and experience

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.

Position of Trust
This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.