Foundational IP Platform Requirements Engineer

Job Description

About the Foundry Technology Development Group:

Foundry Technology Development (Foundry TD) is the heart and soul of Moore’s Law at Intel, enabling Intel to create world-changing technology that enriches the lives of every person on earth. Foundry TD’s more than 13,000 employees drive breakthrough research, develop next generation process and packaging technologies, while also running high volume manufacturing operations in its state-of-the-art facilities in Oregon and Arizona.

The Design Enablement team in Foundry TD works closely with the technology team to maximize the value proposition of the technology for our customers thru Design Technology Co-Optimization (DTCO) and delivers the Process Design Kits (PDKs) and Foundational IP (FIP) that designers need to support their product design work and fully leverage the technology.The DE organization scope includes technology design rules & models, technology and IP testchips, Process Design Kits (PDKs) and Foundational IP.The Foundational IP team is responsible for developing the essential building blocks for Intel’s advanced nodes.This includes Digital, Memory, and GPIO/mixed-signal IP solutions.FIP is the cornerstone of a Foundry’s technology offering.It is essential for technology definition, yield development, and for achieving the best time-to-market for customers on a new technology node.

About the Role:

The Foundational IP Group is responsible for developing leadership IPs that power winning products for our customers and for Intel. The Foundational IP Platform Requirements team is responsible for the definition of Platform PVTs, views, and roadmap requirements. This team will also work closely with our customers and with the Foundational IP engineering teams to ensure that we are delivering best-in-class Foundational IP with consistent quality across the FIP deliverables.

Responsibilities Include:

• Conceptualizes, documents, and designs tools, flows, and methods (TFM) for use in the physical design implementation of IPs, SoCs, and the interaction/handoff/reuse between IPs and SoCs.
• Establishes regression flows, drives improvement in RTL to GDS flows, and creates and implements methodologies for improving robustness, power, performance, area, and timing for optimizing physical design constraints.
• Develops new physical design techniques through innovative scripts, checkers, flows, and other CAD based automation to simplify and expedite the design process.
• Analyzes retrospective data on current generation quality and efficiency gaps to identify proper incremental, evolutionary, or transformative changes to the existing physical design related TFM.
• Partners with physical design, circuits, CAD, RTL, tool/flow owners, and third party vendor teams to continuously improve physical design methodologies and efficiencies.

Qualifications

• Bachelor's or Master's degree in electrical engineering or a similar field.
• 9+ years of experience in the development of foundational IP in the semiconductor industry

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Other Locations

US, OR, Hillsboro; US, CA, Santa Clara

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.



Annual Salary Range for jobs which could be performed in US, California: $162,041.00-$259,425.00
*Salary range dependent on a number of factors including location and experience

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.