Job Description The candidate will be part of graphics pre-silicon validation team under Visual Technologies Teams VTT responsible for pre-silicon validation of the graphics IPs developed for Intel's CPUs/ SOCs . In this position, the candidate will primarily work on functional/performance/power feature verification using the simulation/emulation or formal techniques. Responsibilities include but not limited to:1.Participate in Arch/Micro-arch discussions to develop test plan/test content2.Validation of functional features of the Graphics IP to meet the sign-off metrics and own the sign-off for validation3.Support post-silicon validation teams for content enablement on ATE & yield-improvement .4.Develop new verification flows/methodologies to address the increasing verification complexity
Must possess a minimum of a BS or MS in Electrical Engineering with at least 3-12 years of hands-on experience in pre-silicon validation simulation/emulation/formal . Strong knowledge of Verification flows & methodologies with exposure to SV/UVM and latest Debug tools. Strong debug/problem-solving and communication skills. Ability to effectively work with cross-geo/functional teams. Exposure to graphics / media architecture will be an advantage .Advanced Unix scripting and programming in C*/C++* or Perl/ TCL*. Strong logic design skills and experience in System Verilog / Verilog / VHDL desired
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.