Design of digital and analog circuits for the implementation of the clock distribution network including supporting IP blocks. Today clock network performance is critical for the SoC performance required to support dynamic range for frequencies, reaching high frequencies, low skew and duty cycle errors. The designs are done to support Intel's most advanced client CPUs, using the most updated design tools and the fastest silicon process available today.
1. BSc in Electrical or Computer Engineering
2.Experience in static timing analysis and synthesis.
3. good understanding of VLSI circuit design, innovation, multi-disciplinary design skills tools, ckt, analog, logic, system eng, strong drive ability and team player .
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.