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Job ID: JR0053399
Job Category: Engineering
Primary Location: Hudson, MA US
Other Locations:
Job Type: Experienced Hire

IP Validation Engineer

Job Description

This is an excellent opportunity for a creative and motivated engineer to be part of Scalable Performance CPU Development Group SDG team doing exciting work in the development of next generation microprocessors.

This role offers a platform for the engineer to take his/her validation skills to the next level. In this position, your responsibilities may include but not limited to:

  • Ensuring the logical design of a microprocessor satisfies the architectural specification
  • Creating and optimizing the validation environment, tools and methodologies
  • Developing or using checking software to compare model behavior against a specification
  • Generating focused/random test cases, develop/analyze coverage and debugging failure cases
  • Writing software to provide controllability and observability into the architectural model

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Additional responsibilities, may include:

  • Oversee definition, design, verification, and documentation for SoC System on a Chip development
  • Determine architecture design, logic design, and system simulation
  • Define module interfaces/formats for simulation
  • Perfor Logic design for integration of cell libraries, functional units and subsystems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs
  • Contribute to the development of multidimensional designs involving the layout of complex integrated circuits
  • Perform all aspects of the SoC design flow from high level design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing
  • Analyze equipment to establish operation infrastructure, conducts experimental tests, and evaluates results
  • May also review vendor capability to support development


Qualifications

Minimum Qualification:

  • BS or MS degree in Electrical or Computer Engineering or related fields
  • 4-8 years of solid IP validation experience
  • Strong experience in creating and optimizing the complex validation environment and generating focused and random test cases, analyzing coverage and debugging failure cases
  • Strong problem solving and debugging skills and ability to work closely with various chip design disciplines and cross site teams
  • Proven verbal and written communication skills
  • Motivated, self-directed and able to work effectively both independently and in a team environment

Preferred Qualifications:

  • 4+ years of experience performing IP and/or SoC functional validation using System Verilog
  • 1+ years of experience in UVM/OVM
  • Experience using scripting languages in design automation using with languages such as TCL, Perl, JSON, Python

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.


Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.
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