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Job ID: JR0053096
Job Category: Engineering
Primary Location: Hudson, MA US
Other Locations:
Job Type: Experienced Hire

SOC Design Engineer Manager

Job Description
  • As a manager, set priorities for the team, get results across boundaries, ensure an inclusive work environment, develop employees, and manage performance.
  • Oversees definition, design, verification, and documentation for SoC System on a Chip development.
  • Determines architecture design, logic design, and system simulation.
  • Defines module interfaces/formats for simulation.
  • Performs Logic design for integration of cell libraries, functional units and subsystems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs.
  • Contributes to the development of multidimensional designs involving the layout of complex integrated circuits.
  • Performs all aspects of the SoC design flow from highlevel design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing.
  • Analyzes equipment to establish operation infrastructure, conducts experimental tests, and evaluates results.
  • May also review vendor capability to support development.
  • Selects, develops, and evaluates SoC design engineers to ensure the efficient operation of the function.


Qualifications

Required Skills/Experience

  • BS or MS in Electrical Engineering, Computer Science, Computer Engineering, or other related field
  • 5+ years of hands-on experience track-record of success in pre-silicon logic and validation to provide basis for management judgment and schedule management
  • 3+ years First line management of engineers
  • Setting goals, schedule and staging plans along with tracking and enabling execution for team
  • Prior Contributing to organizations longer-term technical visions – Candiaet should have some of the following experience (not necessairly all) * Design and develop new micro-architecture features to improve IP capabilities* RTL coding and Validation of server features in cluster test environments * Validating designs by authoring validation plans, writing focus tests, creating templates defining coverage strategies, developing and analyzing coverage monitors, creating event injectors, writing architectural and micro-architectural correctness checkers, developing BFMs Bus Functional Model, running functional simulations, and debugging failures to root cause * Maintaining and enhancing the validation infrastructure by creating new tools to support validation.
  • Must be willing to work in Hudson, Massachusetts

Preferred Skills/Experience

  • Prior experience in chip design

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.


Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.
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