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Job ID: JR0051317
Job Category: Engineering
Primary Location: Folsom, CA US
Other Locations:
Job Type: Experienced Hire

Pre-Silicon Reliability Engineer

Job Description

As a member of the Design team focusing on ESD Quality and Reliability you will be responsible for working with Device, Design, Design Automation, and Layout personnel in defining, developing, and delivering key company and customer ESD and Latchup reliability objectives, including;

  • The direct execution of, or the assisting/training of others, in the pre-silicon ESD validation checks, to ensure that the product meets spec and quality objectives
  • Making recommendations to Device, Design, DA, and Layout regarding the changes and/or the mitigation required to achieve a quality output/product
  • The development of new, and the maintenance of existing pre-silicon ESD validation flows, and the documentation of same
  • The taking of lab data to help close the loop between pre-silicon validation results and post-silicon results
  • Validation of the pre-silicon ESD checks, which requires a good physical understanding of the phenomena under test, as well as, the measurement and comparison to post-silicon results
  • The continuous improvement of ESD quality and reliability
  • Managing the schedule and delivery/development of new ESD checks and the execution of same.


Qualifications

The candidate should have as a minimum a BS in Physics, EE, or other technical area. The ideal Pre-Silicon Reliability Engineering candidate would have 10+ years of related experience and some knowledge of the following:

  • Circuit related
    • A good basic understanding of MOS transistor operation and circuit design
    • A basic understanding of MOS transistor layout design and parasitics
    • Experience using circuit simulation tools such as HSPICE, XA, Spectre, …
  • Back-End CAD tools
    • PERC:                                                 Mentor PERC, Cadence PVS, …
    • ESD:                                                    Totem Pathfinder, …
    • Parasitic Extraction tools:             StarRC, xRC, Totem, …
  • Software and Programming tools
    • Languages/tools:                            Python, TCL, excel/office, wiki, …
  • Design Environments
    • Schematic & Layout tools:            Cadence Virtuoso, Synopsys CustomDesigner, …
  • ESD & Latchup specific knowledge unique to NAND memory products:
    • A good working knowledge of ESD device operation and failure mechanisms for a variety of circuit situations
    • A good working knowledge of the Latchup phenomena and the safeguards required to avoid it
    • Knowledge of the required/preferred Layout and DRC rules for ensuring quality ESD and LatchUp performance
    • Knowledge of current industry standards/specifications (pass/fail criteria), tools, methods, and practices employed
      • Knowledge regarding the application of the HBM, MM, or CDM requirement
    • EOS/ESD Association ESD training/certification
    • The knowledge and experience required to put into place complete ESD and LatchUp sign-off methodologies
    • An understanding of the tradeoffs when prioritizing the fixes identified by the ESD and LatchUp checks
      • Familiarity with one or more of the following ESD tools: Totem Pathfinder, Sigrity, …
    • Knowledge regarding the effect/interaction of the die package, stacked die, and the PCB on die ESD performance
    • Skill in the generation and use of Transmission Line Pulse (TLP) and VeryFastTLP (vfTLP) hardware models
    • Skill in reviewing proposed layouts and the quick identification of problematic changes made to the baseline ESD structure
    • Skill in the design and execution of, experiments and test structures, required to validate changes made in order to improve overall ESD performance
    • Skill in the laboratory study of ESD performance including Failure Analysis (FA) and Fault Isolation (FI) of silicon ESD failures, and the familiarity with:
      • Scanning Electron Microscope (SEM), Emission Microscopy (EMMI), and Focused Ion Beam (FIB) editing
      • Test equipment required for studying ESD and Latchup phenomena including;
        • HP Semiconductor Parameter Analyzer, Oscilloscopes, …
        • ESD testers (Keytek, Botron, SCS, …)
        • Probe station and Assembled part testing setups

Inside this Business Group

Non-Volatile Solutions Memory Group:  The Non-Volatile Memory Solutions Group is a worldwide organization that delivers NAND flash memory products for use in Solid State Drives (SSDs), portable memory storage devices, digital camera memory cards, and other devices.  The group is responsible for NVM technology design and development, complete Solid State Drive (SSD) system hardware and firmware development, as well as wafer and SSD manufacturing.


Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.
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