Responsible for ensuring the testability and manufacturability of integrated circuits from Presilicon development stage through production ramp. Make significant contributions to DFT design definition, development and validation towards high testability of digital circuits. Perform evaluation and development of new DFT test methodology to meet guaranteed specification and screen defects on silicon which meets Intel's product quality commitment. Analyze early customer returns with emphasis on driving test hole closure activities through partnership with other teams. Creates and applies new technology for optimizing component production relative to both quality and cost constraints. Will be given the opportunity to grow leadership skills, expose to a vast networking platform and collaborate with different stakeholders across the world.
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.