As a senior member of the VTT Graphics DFx group, you will be responsible for the following activities: You will work on the RTL design, RTL/GLS validation, automation, and/or timing analysis in one of the following DFx domains: Controller, Scan, Array DFT, Functional DFT, or DFD.You will also contribute or be involved with trace/pattern generation efforts as well as post-silicon enabling, debug support, and/or analysis of the DFx features/content types you are responsible for .
Candidate must have a BS with 6+ years of experience OR MS in Electrical Engineering or related field with 4+ years working experience.
Candidate should have 4+ years with the following:
Strong understanding and working knowledge of key DFx features such as Controller, Scan, Array DFT, Functional DFT, or DFD one of these areas is required.
Good knowledge/experience in the following ASIC design and/or validation areas:Working knowledge/experience with a scripting language such as Perl.Working knowledge/experience in Verilog and/or System Verilog.
Experience with RTL/GLS simulation/environment using industry standard simulator e.g. VCS/modelsim. Experience with Structural Design flows such as timing, routing, placement, or clocking analysis.
Good knowledge/experience with post-silicon enabling/debug of the DFx features at least a few of the following:Experience with High Volume Manufacturing HVM.Knowledge of tester platforms.Experience with Manufacturing data analysis.Knowledge of the SV debug requirements.
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.