Intel's ITG-MIG organization empowers Intel SOCs with leading mixed-signal IP. The Toronto analog design team within MIG is looking for talented individuals who wish to be a part of building the Industry's next generation products with focus on high-speed serial links.
Analyze performance of high-speed serial links at system level
Build, validate and maintain behavioral models of high-speed serial link components
Work with various groups to facilitate IP verification across analog/digital boundaries
Analyze and optimize SerDes calibration and adaptation algorithms
Perform signal integrity analysis to support SerDes IP customers and design teams
Document system validation practices and procedures
Ph.D. or M.A.Sc. in electrical/communication engineering with 3+ years of experience.
Strong background in serial link fundamentals, communications theory, linear systems analysis
Good understanding of signal integrity concepts
Working experience using Matlab and Simulink
Experience with signal integrity EDA tools and simulations: SiSoft QCD, Keysight ADS
Understanding of IBIS AMI standard and simulation flow is an asset
Able to work independently with limited supervision
Understanding of analog and mixed signal circuit design concepts
Experience debugging, probing, and characterizing silicon using standard lab equipment
Knowledge of Verilog-A for analog behavioral modeling is an assetKnowledge of digital signal processing
Experience with C/C++, Perl, Python or other programming and scripting languages is desired
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.