Job Description In this position, you will be part of the R&D team chartered to deliver IP and subsystem design and verification to SOC team across Intel for latest products ranging from server, desktop, tablet, to IOT and wearables. Your responsibilities include front-end design coding, assertion coding, ensure design quality by running RTL quality checks, interfacing with synthesis/timing analysis team to ensure timing clean design. The employee needs to be flexible to develop testbench, verification collaterals such as scoreboard, behavioral model, tracker/checker, and validate the functionality of RTL design by developing testplan, tests sequences, coverage point or test tools.
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.