As a Pre-Si DV engineer, you will be an owner of one or more architectural functional block to perform all DV related tasks including test plan development, implementation, test bench, test stimuli, and collaborate with RTL designer to identify coverage gaps and functional bug closure. Previous pre-silicon system verification experience in at least one of the following areas including SoC, FPGA, Sub-system, or Full Chip design verification. Create test case and test bench using UVM methodology. Be part of the team that carries out Full chip and/or system functional verification where the team will define verification strategies, methodology and test plan to enable effective verification. Be part of team that collaborate cross functional efforts with Design, SW, Architecture team to achieve full coverage verification plan.
You should possess a Bachelor's and/or a Master's degree in Electronics and/or Electronics and Communication and/or Very Large Scale Integration VLSI area. Additional qualifications include: More than 10+ years of VLSI Front-end experience - Sound understanding of functional verification fundamentals encompassing state machine verification, complex protocol verification, functional test strategies, directed and stress test generation, verification infrastructures and verification and/or debug flows - Gate level simulations - Adept in programming and/or scripting C++, Perl* and others and be conversant with flows and tools for VLSI logic design and/or functional verification - Excellent written and verbal communication skills - Person in this role is expected to execute the verification activity at cluster level as well as Full Chip, SOC level - Good knowledge on functional and code coverage - Drive the overall verification methodology using HVLs like system Verilog The following qualifications would be added advantages: - In depth knowledge of System Verilog and verification methodologies like OVM Working experience on the PCIe, SATA, OCP, UART-Working knowledge of modern PC architecture Specific IO architecture knowledge is a plus - Extensive knowledge of System Verilog and working knowledge of verification methodologies like OVM and others.Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.