Analog Design Engineer
This position is for an analog designer that will be part of a leading PLL Phase Locking Loop design team. The team designs in the front of the technology: Leading industry process and cutting edge of innovative PLL circuits. The team delivers PLL systems to other Intel teams, and are responsible for design and validation from architecture definition all the way to productized PLL in a commercial product. The designer will take part in the various activities that are done within the team: Design, validation and integration of the building blocks, analysis and validation on to the PLL system and wrapping up and delivering the hard-IP to other design teams. Post manufacturing verification and debugging is also done by the PLL team. The position will be an integral part of the development team. The work is done in a small and excellent team.
Inside this Business Group
* Electrical engineering or equivalent degree.* Candidate is expected to have over 5y experience outstanding inexperienced will also be considered in analog design.* Experience with PLLs is an advantage.
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.