Job Description The candidate will be responsible for leading major cluster/top level implementation, delivering RTL, micro-architectural specification documentation and working with cross-functional engineering teams on simulation, design and verification.DescriptionAs a Lead RTL engineer you will own or participate in the following: RTL ownership - Development, assessment and refinement of RTL design to target power, performance, area and timing goals. Validation - Support testbench development and simulation for functional and performance verification. Performance exploration and correlation - Explore high performance strategies and validate that the RTL design meets targeted performance. Design delivery - Work with cross-functional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability and power. Lead a team of junior engineers in verification tasks
-The candidate should possess a B.Sc or M.Sc in Computer or Electrical Engineering with 7+ years of RTL experience.-Knowledge of Verilog and/or VHDL. Experience with simulators and waveform debugging tools.-Knowledge of logic design principles along with timing and power implications.-Understanding of low power microarchitecture techniques.-Experience using an interpretive language such as Perl, Python or Ruby.-EducationBSEE/MSEE is required
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.