We are looking for a talented Practical Engineer to work as Physical Layout Designer.
The role including Layout synthesis editing (ICC synopsis) Floor plan and verification of VLSI circuits and Design Rules checkers.
Target is to convergence with correlation to extraction results and process constrains.
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.