Job Description Develop and refine digital logic blocks for High Speed Serial IOs. Understand and run front-end tools for CDC, LINT, Low-power structural checks on the functional units. Simulate the design, debug issues and provide RTL solution. Understand analog blocks, its behavioral models, digital-analog interface. Integrate PHY families by combining logic and analog models.
BS or MS with 1+ years of experience in high performance ASIC Development. Experience in Verilog, System Verilog digital design, simulation and verification. Experience with VCS, Verdi, Spyglass or equivalent tools. Knowledge about low-power design, UPF, synthesis, formal verification, static timing analysis are plus.
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.